pulsar_adc: add split transfer functionality

add two parameters, USE_SPLIT_TRANSFERS and SPLIT_SIZE, to enable split transfers. If USE_SPLIT_TRANSFERS is set to 1, an asymetric fifo is used to stitch together 2 transfers before sending them to the DMA. SPLIT_SIZE is used to indicate the size of each transfer in the split, and is obligatory if USE_SPLIT_TRANSFERS is selected; otherwise an error will happen. Signed-off-by: Laez Barbosa <[email protected]>
analogdevicesinc · Sep 26, 2024 · c08ce80 · c08ce80
1 parent f40ad56
commit c08ce80
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Showing 3 changed files with 36 additions and 1 deletion.
diff --git a/projects/pulsar_adc/common/pulsar_adc_bd.tcl b/projects/pulsar_adc/common/pulsar_adc_bd.tcl
@@ -15,6 +15,9 @@ set num_sdo       1
 set sdi_delay     1
 set echo_sclk     0
 
+set USE_SPLIT_TRANSFERS [get_env_param USE_SPLIT_TRANSFERS 0]
+set SPLIT_SIZE [get_env_param SPLIT_SIZE 0]
+
 set hier_spi_engine spi_pulsar_adc
 
 spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
@@ -40,6 +43,24 @@ ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_2D_TRANSFER 0
 ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width
 ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64
 
+if {$USE_SPLIT_TRANSFERS == 1} {
+    ad_ip_instance util_axis_fifo_asym rx_asym_fifo
+    ad_ip_parameter rx_asym_fifo CONFIG.ASYNC_CLK 0
+    ad_ip_parameter rx_asym_fifo CONFIG.S_DATA_WIDTH $SPLIT_SIZE
+    ad_ip_parameter rx_asym_fifo CONFIG.S_ADDRESS_WIDTH 3
+    ad_ip_parameter rx_asym_fifo CONFIG.M_DATA_WIDTH [expr {2*$SPLIT_SIZE}]
+    ad_ip_parameter rx_asym_fifo CONFIG.M_AXIS_REGISTERED 1
+    ad_ip_parameter rx_asym_fifo CONFIG.ALMOST_EMPTY_THRESHOLD 2
+    ad_ip_parameter rx_asym_fifo CONFIG.ALMOST_FULL_THRESHOLD 6
+    ad_ip_parameter rx_asym_fifo CONFIG.TLAST_EN 0
+    ad_ip_parameter rx_asym_fifo CONFIG.TKEEP_EN 0
+
+    ad_connect spi_clk rx_asym_fifo/s_axis_aclk 
+    ad_connect $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn rx_asym_fifo/s_axis_aresetn
+    ad_connect spi_clk rx_asym_fifo/m_axis_aclk 
+    ad_connect $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn rx_asym_fifo/m_axis_aresetn
+}
+
 ad_connect $sys_cpu_clk spi_clkgen/clk
 ad_connect spi_clk spi_clkgen/clk_0
 
@@ -48,7 +69,12 @@ ad_connect $sys_cpu_clk pulsar_adc_trigger_gen/s_axi_aclk
 ad_connect sys_cpu_resetn pulsar_adc_trigger_gen/s_axi_aresetn
 ad_connect pulsar_adc_trigger_gen/pwm_0 $hier_spi_engine/trigger
 
-ad_connect axi_pulsar_adc_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
+if {$USE_SPLIT_TRANSFERS == 1} {
+    ad_connect rx_asym_fifo/s_axis $hier_spi_engine/M_AXIS_SAMPLE
+    ad_connect axi_pulsar_adc_dma/s_axis rx_asym_fifo/m_axis
+} else {
+    ad_connect axi_pulsar_adc_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
+}
 ad_connect $hier_spi_engine/m_spi pulsar_adc_spi
 
 ad_connect $sys_cpu_clk $hier_spi_engine/clk

diff --git a/projects/pulsar_adc/zed/Makefile b/projects/pulsar_adc/zed/Makefile
@@ -28,5 +28,6 @@ LIB_DEPS += spi_engine/spi_engine_interconnect
 LIB_DEPS += spi_engine/spi_engine_offload
 LIB_DEPS += sysid_rom
 LIB_DEPS += util_i2c_mixer
+LIB_DEPS += util_axis_fifo_asym
 
 include ../../scripts/project-xilinx.mk
diff --git a/projects/pulsar_adc/zed/system_project.tcl b/projects/pulsar_adc/zed/system_project.tcl
@@ -24,6 +24,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 ##    0 - EVAL-ADAQ400x
 ##
 set AD40XX_ADAQ400X_N [get_env_param AD40XX_ADAQ400X_N 1]
+set USE_SPLIT_TRANSFERS [get_env_param USE_SPLIT_TRANSFERS 0]
+set SPLIT_SIZE [get_env_param SPLIT_SIZE 0]
 
 adi_project pulsar_adc_pmdz_zed
 
@@ -43,4 +45,10 @@ if {$AD40XX_ADAQ400X_N == 0} {
   return -code error [format "ERROR: Invalid eval board type! ..."]
 }
 
+if {$USE_SPLIT_TRANSFERS == 1} {
+  if {$SPLIT_SIZE == 0} {
+    return -code error [format "ERROR: missing size for split transfers! ..."]
+  }
+}
+
 adi_project_run pulsar_adc_pmdz_zed