V2: axi_dmac: Sanitize bit ops and comb logic

Sanitize bitwise operators and combinational logic to avoid mixing them in the same statement. Signed-off-by: Jorge Marques <[email protected]>
analogdevicesinc · Jul 16, 2024 · da7182a · da7182a
1 parent d728cfd
commit da7182a
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Showing 3 changed files with 14 additions and 14 deletions.
diff --git a/library/axi_dmac/axi_dmac_ext_sync.v b/library/axi_dmac/axi_dmac_ext_sync.v
@@ -104,7 +104,7 @@ module axi_dmac_ext_sync #(
       end
     end
 
-    assign req_ext_sync = req_src_ext_sync || req_dest_ext_sync;
+    assign req_ext_sync = req_src_ext_sync | req_dest_ext_sync;
     assign ext_sync_ready = ext_sync_ready_s;
 
   end else begin

diff --git a/library/axi_dmac/axi_dmac_framelock.v b/library/axi_dmac/axi_dmac_framelock.v
@@ -99,7 +99,7 @@ module axi_dmac_framelock #(
   always @(posedge req_aclk) begin
     if (req_aresetn == 1'b0) begin
       prev_buf_done <= 1'b1;
-    end else if (out_req_valid & out_req_ready) begin
+    end else if (out_req_valid && out_req_ready) begin
       prev_buf_done <= 1'b0;
     end else if (resp_eot) begin
       prev_buf_done <= 1'b1;
@@ -120,7 +120,7 @@ module axi_dmac_framelock #(
     if (req_aresetn == 1'b0) begin
       transfer_id <= 'h0;
       req_address <= 'h0;
-    end else if (req_valid & req_ready) begin
+    end else if (req_valid && req_ready) begin
       transfer_id <= 'h0;
       req_address <= FRAMELOCK_MODE ? req_src_address : req_dest_address;
     end else if (calc_enable) begin
@@ -137,7 +137,7 @@ module axi_dmac_framelock #(
   // Latch the transfer IDs so it can be passed to the reader
   // once it is completed
   always @(posedge req_aclk) begin
-    if (out_req_valid & out_req_ready) begin
+    if (out_req_valid && out_req_ready) begin
       cur_frame_id <= transfer_id;
     end
   end
@@ -147,13 +147,13 @@ module axi_dmac_framelock #(
       req_ready <= 1'b1;
     end else if (req_ready == 1'b1) begin
       req_ready <= ~req_valid;
-    end else if (out_req_valid & out_req_ready) begin
+    end else if (out_req_valid && out_req_ready) begin
       req_ready <= ~req_cyclic;
     end
   end
 
   always @(*) begin
-    out_req_valid = calc_enable & (calc_done || ~req_flock_en);
+    out_req_valid = calc_enable & (calc_done | ~req_flock_en);
   end
 
   generate if (FRAMELOCK_MODE == 0) begin
@@ -172,7 +172,7 @@ module axi_dmac_framelock #(
     always @(posedge req_aclk) begin
       if (req_aresetn == 1'b0) begin
         reader_started <= 1'b0;
-      end else if (req_valid & req_ready) begin
+      end else if (req_valid && req_ready) begin
         reader_started <= 1'b0;
       end else if (~req_ready) begin
         if (s_frame_id_vld) begin
@@ -187,9 +187,9 @@ module axi_dmac_framelock #(
     assign s_frame_id = m_frame_in[MAX_NUM_FRAMES_WIDTH-1:0];
     assign s_frame_id_vld = m_frame_in[MAX_NUM_FRAMES_WIDTH];
 
-    assign calc_done = s_frame_id != transfer_id ||
-                       reader_started == 1'b0 ||
-                       req_flock_mode == 1'b1;
+    assign calc_done = (s_frame_id != transfer_id ||
+                        reader_started == 1'b0 ||
+                        req_flock_mode == 1'b1);
   end else begin
 
     // Reader mode logic
@@ -220,7 +220,7 @@ module axi_dmac_framelock #(
     always @(posedge req_aclk) begin
       if (req_aresetn == 1'b0) begin
         wait_distance <= 1'b1;
-      end else if (req_valid & req_ready) begin
+      end else if (req_valid && req_ready) begin
         wait_distance <= req_cyclic && req_flock_en;
       end else if (~req_ready) begin
         if (({1'b0, m_frame_id} == req_flock_distance) && m_frame_id_vld) begin
@@ -288,8 +288,8 @@ module axi_dmac_framelock #(
     // until the writer completes a buffer. In Dynamic Flock just wait until
     // the required number of buffers are filled, then enable the request
     // generation regardless of the writer.
-    assign enable_out_req = req_flock_wait_writer == 1'b0 ||
-                            ((m_frame_ready | ~req_flock_mode) & ~wait_distance);
+    assign enable_out_req = (req_flock_wait_writer == 1'b0 ||
+                             ((m_frame_ready | ~req_flock_mode) & ~wait_distance));
 
   end
   endgenerate

diff --git a/library/axi_dmac/dmac_2d_transfer.v b/library/axi_dmac/dmac_2d_transfer.v
@@ -197,7 +197,7 @@ module dmac_2d_transfer #(
     end
   end
 
-  assign out_req_last = (out_last || (DMA_2D_TLAST_MODE == 1)) & gen_last;
+  assign out_req_last = (out_last | (DMA_2D_TLAST_MODE == 1)) & gen_last;
   assign out_req_islast = out_last;
 
 endmodule