Added support for AD3552R #1086

PopPaul2021 · 2023-02-20T09:43:20Z

V1: Tested on ZedBoard.

PopPaul2021 · 2023-02-20T09:54:56Z

V2: After guideline check.

library/axi_ad3552r/Makefile

library/axi_ad3552r/axi_ad3552r_channel.v

library/axi_ad3552r/axi_ad3552r_if_tb

library/axi_ad5766/axi_ad5766.v

library/common/up_dac_channel.v

library/common/up_dac_common.v

PopPaul2021 · 2023-02-21T09:40:39Z

V3: After review updates and reference clock was updated to 133.3 MHz.

PopPaul2021 · 2023-03-01T08:39:27Z

V4: Cosmetic updates after review.

acostina

The regmap files should be updated with the new capabilities.

The cosmetic commit should be squashed with the IP commit

PopPaul2021 · 2023-03-01T15:53:47Z

V4: Cosmetic squashed and adi_regmap_dac updated.

PopPaul2021 · 2023-03-14T08:17:29Z

V5: Testbench cosmetics and rebase.

PopPaul2021 · 2023-03-28T12:33:17Z

V6: After rebasing and renaming the VCD_FILE in axi_ad3552r_if_tb.v.

acostina

The project looks good.

The board page in the link https://www.analog.com/en/products/eval-ad3552r.html should be modified to https://www.analog.com/eval-ad3552r

Is there any documentation on wiki ?

projects/ad3552r_evb/zed/system_top.v

PopPaul2021 · 2023-05-08T14:17:04Z

V7: Updates after revision. The multiple device synchronization feature has been synchronized in the AD3552R interface IP.

PopPaul2021 · 2023-05-10T06:27:24Z

V8: After deleting the tb_base.v file and change the include location to library/common/tb/tb_base.v.

acostina

Looks good.
Should wait for the software to be ready before merging

PopPaul2021 · 2023-05-10T12:06:19Z

V9: After updating the copyright start year.

PopPaul2021 · 2023-05-16T07:02:08Z

Project Wiki pages:
EVAL-AD3552R Evaluation Board on ZedBoard User Guide
AXI_AD3552R IP
AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Linux device driver

PopPaul2021 · 2023-05-16T07:56:34Z

V10: After updating the Readme.md Wiki page links.

PopPaul2021 · 2023-06-26T12:27:25Z

V11: After adding the DDS option as an input source. The updates were tested by manually configuring the DDS registers.

acostina

Looks good.
Added some comments

acostina · 2023-08-14T06:53:16Z

projects/ad3552r_evb/Readme.md

+  * Project Doc: https://wiki.analog.com/resources/eval/eval-ad3552r-user-guide
+  * HDL Doc: https://wiki.analog.com/resources/eval/eval-ad3552r-user-guide


These links should point to the User Guide that uses this project

Solved in V12.

acostina · 2023-08-14T06:59:17Z

library/axi_ad3552r/axi_ad3552r_channel.v

+  assign dac_data_int = (dac_data_sel_s == 4'hb) ? ramp_pattern :
+                        ((dac_data_sel_s == 4'h3) ? 16'b0 :
+                        (((dac_data_sel_s == 4'h8) ? formatted_adc_data :
+                        ((dac_data_sel_s == 4'h2) ? formatted_dma_data: dac_dds_data_s ))));
+
+  assign dac_data_valid_int = (dac_data_sel_s == 4'hb) ? ramp_valid :
+                              ((dac_data_sel_s == 4'h3) ? 1'b1 :
+                              (((dac_data_sel_s == 4'h8) ? valid_in_adc :
+                              ((dac_data_sel_s == 4'h2) ? valid_in_dma: 1'b1 ))));
+


Given that there is no need for priority, should we implement this as case ?

Solved in V12.

library/axi_ad3552r/axi_ad3552r_core.v

PopPaul2021 · 2023-09-20T14:55:24Z

V12: After updating copyrights and solving review suggestions.

The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.

The custom interface IP for AD3552R DAC has more operation capabilities: - 8b register read/write SDR/DDR - 16b register read/write SDR/DDR - data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate) - selectable input source : DMA/ADC/TEST_RAMP - data out clock(SCLK) has clk_in/8 frequency when the converter is configured and clk_in/2 when the converter is in stream mode - the IP reference clock (clk_in) can have a maximum frequency of 132MHz - the IP has multiple device synchronization capability when the DMA is set as an input data source Signed-off-by: PopPaul2021 <[email protected]>

The project controls the AD3552R digital-to-analog converter and transmits data written in the DDR memory to the QSPI interface of the DAC. The reference clock is generated by an axi_clkgen IP and is configured to output a 133MHz signal. If both channels are enabled and data streaming is DDR the sample rate is 16.65MSPS. If just one channel is enabled and data streaming is DDR the sample rate is 33.3MSPS. The VADJ voltage should be set to 1.8V. Signed-off-by: PopPaul2021 <[email protected]>

PopPaul2021 force-pushed the axi_ad3552r_fmc_dev branch from 2f1ae05 to c06f5b5 Compare February 20, 2023 09:54

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PopPaul2021 requested review from acostina, IuliaCMoldovan and alin724 March 16, 2023 08:48

IuliaCMoldovan previously approved these changes Mar 16, 2023

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PopPaul2021 dismissed IuliaCMoldovan’s stale review via 5a51cfe March 28, 2023 11:03

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acostina reviewed Apr 28, 2023

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PopPaul2021 force-pushed the axi_ad3552r_fmc_dev branch 2 times, most recently from a2050c5 to de41c26 Compare May 8, 2023 14:15

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PopPaul2021 requested review from podgori and AndreiGrozav as code owners September 20, 2023 14:33

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PopPaul2021 added 3 commits October 2, 2023 10:03

library/common: Added DAC custom read/write interface in up_dac_common.

41f4d39

The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.

PopPaul2021 force-pushed the axi_ad3552r_fmc_dev branch from 6279c2a to debbc3e Compare October 2, 2023 07:05

acostina approved these changes Oct 2, 2023

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PopPaul2021 merged commit c29c092 into master Oct 2, 2023
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PopPaul2021 deleted the axi_ad3552r_fmc_dev branch October 2, 2023 08:07

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Added support for AD3552R #1086

Added support for AD3552R #1086

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PopPaul2021 commented Sep 20, 2023

		* Project Doc: https://wiki.analog.com/resources/eval/eval-ad3552r-user-guide
		* HDL Doc: https://wiki.analog.com/resources/eval/eval-ad3552r-user-guide

Added support for AD3552R #1086

Added support for AD3552R #1086

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