I3c controller #1129
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I3c controller #1129
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Include library files for the I3C Controller. "not_formatted" folder are hdl files that have not yet been incorporated into the library and do not follow the guidelines, e.g. not_formatted/src/mod_bit.v -(will be integrated to)-> i3c_controller_core/i3c_controller_bit_mod.v Signed-off-by: Jorge Marques <[email protected]>
Include i3c_controller_write_byte to pack u8 data into u32 SDI FIFO and update i3c_controller_read_byte to unpack u8 data from u32 SDO FIFO. Signed-off-by: Jorge Marques <[email protected]>
Change resetn to reset_n to match coding quidelines. Add module to generate quarter clock for I3C bit modulation. Signed-off-by: Jorge Marques <[email protected]>
Preparing for implementing Command Parsed logic. Can generate the block diagram. Signed-off-by: Jorge Marques <[email protected]>
Project using the I3C Controller (not mentioning any specific part). Signed-off-by: Jorge Marques <[email protected]>
Modulates bits to be sent in the I3C bus, with open-drain or push-pull modes. Signed-off-by: Jorge Marques <[email protected]>
Signed-off-by: Jorge Marques <[email protected]>
Work in progress, this module joins the cmdp and sdio interface into a single cmdw interface that inscructs the word (tbd) module which "word" to send next to the bus. At events when an ACK is not satisfied by a peripheral, the word module will issue a _nack and the state-machine of the framing will reset, cancelling the current word (will never Sr). Signed-off-by: Jorge Marques <[email protected]>
Implements RX/TX private transfer. Next step is to update daa module to use the word module, then implement CCC commands to framing module. Signed-off-by: Jorge Marques <[email protected]>
Update DAA to use Word module, reduncing resource usage. Also fixup bondaries in Word module. Signed-off-by: Jorge Marques <[email protected]>
Use a secondary clock for the bit modulation at 50Mhz. Change the i3c_clk from 200Mhz to 100MHz to ease timing. Use half i3c_clk_bus to modulate Open-Drain words. Signed-off-by: Jorge Marques <[email protected]>
Signed-off-by: Jorge Marques <[email protected]>
Use 8 clock cycles instead of 4 for bit modulation, giving more freedom to meet the requirements of the specification, better windows to sample rx data, check ACK and read T-bit. Signed-off-by: Jorge Marques <[email protected]>
Access to DAA status and addresses through regmap. Implement access to DAA module's status, number of peripheral assigned a DA in the bus, and retrieve the DAs. Include I3C Controller regmap header file to be used in the axi_i3c_controller. Update word command to allow private transfer without broadcasting header. Signed-off-by: Jorge Marques <[email protected]>
Some ready/valid signals where not in "sync" with each other (the data was sampled while to issuing a ready signal, and vice-versa. Changes have been made to mitigate that. Signed-off-by: Jorge Marques <[email protected]>
Update clk_1 frequency to 12.5MHz to achieve viable open-drain transfer speed. Update mod_bit to integrate this higher difference between push-pull and open-drain frequencies; setting up different open-drain~push-pull is now easier. Fixup read and write bytes. Signed-off-by: Jorge Marques <[email protected]>
Include transfered length in the command receipt (cmdr), allowing the driver to know how much bytes to read or check if the controller wrote to the device. Also, fixup clk name in xdc. Signed-off-by: Jorge Marques <[email protected]>
These files are .gitignored by default. Signed-off-by: Jorge Marques <[email protected]>
New command receipt structure to include error and sync field. Signed-off-by: Jorge Marques <[email protected]>
Implement in-band interrupts (IBI) from the I3C implementation. Currently, only the MDB is supported. Signed-off-by: Jorge Marques <[email protected]>
Update to have the same structure as framing module. Fixup IBI to handle both types of IBI requests. Signed-off-by: Jorge Marques <[email protected]>
Instead of using the mmcm to generate the 50MHz clock, obtain a 25MHz clock derived from 100MHz with a prescaler. Also change from the controller clock to syncronous, and use the common clock to drive it. Signed-off-by: Jorge Marques <[email protected]>
Signed-off-by: Jorge Marques <[email protected]>
Integrate device characteristics access in the HDL, allowing to setup the DA and reading the PID, BCR and DCR of the peripherals with register access. Optimizations are needed, for example, MAX_DEVS is not yet as a parameter in the Vivado GUI and BRAM can be used to store the dev_char_*. Signed-off-by: Jorge Marques <[email protected]>
ad_mem_dual is an abstraction to infer dual-port BRAM. The dev_char_* registers can be RW by both sides to reduce logic, however the driver shall only write and read as intended in the interface specification. Signed-off-by: Jorge Marques <[email protected]>
It was a symbolic link by mistake before. Signed-off-by: Jorge Marques <[email protected]>
The offload module is embed in the axi module. Perhaps it would be better to break axi_i3c_controller into multiple submodules like the other modules, since the logic is more complex now. Also, perhaps even merge with the host_controller block. Signed-off-by: Jorge Marques <[email protected]>
There is no guideline for verilog header files, and since they don't contain a module, a warning "no module found" is raised for every verilog header. Signed-off-by: Jorge Marques <[email protected]>
Signed-off-by: Jorge Marques <[email protected]>
Redesign bit modulation module to allow register configurable speed grades. Signed-off-by: Jorge Marques <[email protected]>
Update constraints setting the false path to the worse scenario. Update regmap information. Rename idle_bus to nop, since it is not the bus idle condition, but a flag indicating the bit_mod is not executing any procedure. Signed-off-by: Jorge Marques <[email protected]>
Signed-off-by: Jorge Marques <[email protected]>
Signed-off-by: Jorge Marques <[email protected]>
Update i3c_controller regmap. Include documentation pages for the i3c_controller library. Signed-off-by: Jorge Marques <[email protected]>
Better arbitration handling, check if the received DA is known, and if the IBI requester will send the MDB after the request (BCR[2] == 1). Signed-off-by: Jorge Marques <[email protected]>
Signed-off-by: Jorge Marques <[email protected]>
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Invert speed grade values order. Remove clk_div module. Add DEBUG_IGNORE_NACK parameter to ignore when a transfer is NACKed, useful for testing without a peripheral on the bus, Signed-off-by: Jorge Marques <[email protected]>
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Lock SCL high cycle in 40ns (considering 100MHz clk) for all push-pull speeds, allowing mixed fast bus operation (I3C transfers are filtered by 50ns Spike Filters). There is no change for 12.5ns, since the Low/High width are already 40ns, however, the max speed for mixed fast bus is 8.3MHz due to dc bias. Signed-off-by: Jorge Marques <[email protected]>
Introduce a validade state at framing to check if device is attached and is I²C. Revamp DEVS_CTRL. Do not check DA address during IBI anymore, leave it up to the driver. Signed-off-by: Jorge Marques <[email protected]>
Commit the values to the positional ram at the end of the DAA, both I²C and I3C devices. Signed-off-by: Jorge Marques <[email protected]>
Expand CMDW states to include I²C RX and TX transfers. Since RX transfers cannot be cancelled by the controller, a malformed condition occurs when the peripheral tries to send more bytes than the buffer was setted-up for, causing bytes to de discarded. Signed-off-by: Jorge Marques <[email protected]>
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Implements an I3C controller/master.
Formatted as a library similar to the SPI Engine (multiple IPs grouped).
In summary, the expected features from the I3C spec are:
Work in progress.