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Agilex support for AD9081 #1326
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v2: Fixed guideline checker |
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Looks great, just some very minor nitpicks (mostly headers).
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In addition to Laez review,
I was able to synthesize on 23.2 but not on 24.1.
On 24.1 it fails with the following error:
2024.05.21.15:21:59 Error: set_interface_property ref_clk_fgt_2 EXPORT_OF systemclk.out_refclk_fgt_2: No interface named systemclk.out_refclk_fgt_2.
2024.05.21.15:21:59 Error: set_interface_property ref_clk_in EXPORT_OF systemclk.refclk_fgt: No interface named systemclk.refclk_fgt.
The wiki page does not recommend a quartus version, better include the tested version number.
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A few more details (guideline-related)
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Header updates and cosmetic changes. I had to specify for each file, because the script doesn't check the Tcl files and a few others, as they are in the exception list
Signed-off-by: Bogdan Luncan <[email protected]>
Signed-off-by: Bogdan Luncan <[email protected]>
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v3: Added missing headers, updated years and removed extra newlines. Compiles fine with quartus 24.1:
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Would it be useful to add a warning in the Building the HDL project, saying that the FM87 is supported only from Quartus 24.x? To leave no room for discussions (EZ) |
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v4: Added warning information about the Quartus 24.1 requirement inside the docs. |
ad9081: a10soc: Update to support FM87 changes ad9081: s10soc: Update to support FM87 changes Signed-off-by: Bogdan Luncan <[email protected]>
Signed-off-by: Bogdan Luncan <[email protected]>
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v5: Fixed failing project for a10soc and s10soc due to missing system_project variables |
not failing on quartus 24.1, was probably a license issue.
PR Description
Adds support for JESD204B on Agilex 7 (DK-SI-AGI027FA) and the reference design project for AD9081.
Tested on hardware with 8 lanes, 8 converters and a lane rate of 15 GHz.
User guide: https://wiki.analog.com/resources/eval/user-guides/ad9081/quickstart/fm87
PR Type
PR Checklist