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(CI for #1201) TCL: ad_hpmx_interconnect #1391

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(CI for #1201) TCL: ad_hpmx_interconnect #1391

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deb81d6
adi_board: add support for other AXI master interfaces
liambeguin Oct 18, 2023
e80dd5d
adi_board: ad_hpmx_interconnect: add create_bd_addr_seg logs
liambeguin Oct 18, 2023
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93 changes: 59 additions & 34 deletions projects/scripts/adi_board.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@ package require math

## Global variables for interconnect interface indexing
#
set sys_cpu_interconnect_index 0
set sys_hpc0_interconnect_index -1
set sys_hpc1_interconnect_index -1
set sys_hp0_interconnect_index -1
Expand Down Expand Up @@ -954,55 +953,65 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
## Create an AXI4 Lite memory mapped interface connection for register maps,
# instantiates an interconnect and reconfigure it at every process call.
#
# \param[p_sel] - name of the high speed interface
# valid values are HPM0_FPD, HPM1_FPD, HPM0_LPD
# \param[p_address] - address offset of the IP register map
# \param[p_name] - name of the IP
# \param[p_intf_name] - name of the AXI MM Slave interface (optional)
#
proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
proc ad_hpmx_interconnect {p_sel p_address p_name {p_intf_name {}}} {

global sys_zynq
global sys_cpu_interconnect_index
global use_smartconnect

set i_str "M$sys_cpu_interconnect_index"
if {$sys_cpu_interconnect_index < 10} {
set i_str "M0$sys_cpu_interconnect_index"
set interconnect_name [format "axi_%s_interconnect" [string tolower $p_sel]]

if {[catch {
set interconnect_index [get_property CONFIG.NUM_MI [get_bd_cells $interconnect_name]]
} err]} {
set interconnect_index 0
}
set i_str [format "M%02d" $interconnect_index]

if {$sys_cpu_interconnect_index == 0} {
if {$i_str eq "M00"} {

if {$use_smartconnect == 1} {
ad_ip_instance smartconnect axi_cpu_interconnect [ list \
ad_ip_instance smartconnect $interconnect_name [ list \
NUM_MI 1 \
NUM_SI 1 \
]
ad_connect sys_cpu_clk axi_cpu_interconnect/aclk
ad_connect sys_cpu_resetn axi_cpu_interconnect/aresetn
ad_connect sys_cpu_clk $interconnect_name/aclk
ad_connect sys_cpu_resetn $interconnect_name/aresetn
} else {
ad_ip_instance axi_interconnect axi_cpu_interconnect
ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
ad_ip_instance axi_interconnect $interconnect_name
ad_connect sys_cpu_clk $interconnect_name/ACLK
ad_connect sys_cpu_clk $interconnect_name/S00_ACLK
ad_connect sys_cpu_resetn $interconnect_name/ARESETN
ad_connect sys_cpu_resetn $interconnect_name/S00_ARESETN
}

if {$sys_zynq == 3} {
ad_connect sys_cpu_clk sys_cips/m_axi_fpd_aclk
ad_connect axi_cpu_interconnect/S00_AXI sys_cips/M_AXI_FPD
}
if {$sys_zynq == 2} {
ad_connect $interconnect_name/S00_AXI sys_cips/M_AXI_FPD
} elseif {($p_sel eq "HPM0_FPD") && ($sys_zynq == 2)} {
ad_connect sys_cpu_clk sys_ps8/maxihpm0_fpd_aclk
ad_connect $interconnect_name/S00_AXI sys_ps8/M_AXI_HPM0_FPD
} elseif {($p_sel eq "HPM1_FPD") && ($sys_zynq == 2)} {
ad_connect sys_cpu_clk sys_ps8/maxihpm1_fpd_aclk
ad_connect $interconnect_name/S00_AXI sys_ps8/M_AXI_HPM1_FPD
} elseif {($p_sel eq "HPM0_LPD") && ($sys_zynq == 2)} {
ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD
}
if {$sys_zynq == 1} {
ad_connect $interconnect_name/S00_AXI sys_ps8/M_AXI_HPM0_LPD
} elseif {($p_sel eq "GP0") && ($sys_zynq == 1)} {
ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
}
if {$sys_zynq == 0} {
ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
}
if {$sys_zynq == -1} {
ad_connect axi_cpu_interconnect/S00_AXI mng_axi_vip/M_AXI
ad_connect $interconnect_name/S00_AXI sys_ps7/M_AXI_GP0
} elseif {($p_sel eq "GP1") && ($sys_zynq == 1)} {
ad_connect sys_cpu_clk sys_ps7/M_AXI_GP1_ACLK
ad_connect $interconnect_name/S00_AXI sys_ps7/M_AXI_GP1
} elseif {$sys_zynq == 0} {
ad_connect $interconnect_name/S00_AXI sys_mb/M_AXI_DP
} elseif {$sys_zynq == -1} {
ad_connect $interconnect_name/S00_AXI mng_axi_vip/M_AXI
}
}

Expand All @@ -1022,8 +1031,7 @@ proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
set sys_addr_cntrl_space [get_bd_addr_spaces mng_axi_vip/Master_AXI]
}

set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]

set interconnect_index [expr $interconnect_index + 1]

set p_cell [get_bd_cells $p_name]
set p_intf [get_bd_intf_pins -filter \
Expand Down Expand Up @@ -1105,19 +1113,19 @@ proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
}
}

set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
set_property CONFIG.NUM_MI $interconnect_index [get_bd_cells $interconnect_name]

if {$use_smartconnect == 0} {
ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
ad_connect sys_cpu_clk $interconnect_name/${i_str}_ACLK
ad_connect sys_cpu_resetn $interconnect_name/${i_str}_ARESETN
}
if {$p_intf_clock ne ""} {
ad_connect sys_cpu_clk ${p_intf_clock}
}
if {$p_intf_reset ne ""} {
ad_connect sys_cpu_resetn ${p_intf_reset}
}
ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
ad_connect $interconnect_name/${i_str}_AXI ${p_intf}

set p_seg [get_bd_addr_segs -of [get_bd_addr_spaces -of [get_bd_intf_pins -filter "NAME=~ *${p_intf_name}*" -of $p_hier_cell]]]
set p_index 0
Expand Down Expand Up @@ -1147,6 +1155,7 @@ proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
set p_address [expr ($p_address + 0x20000000)]
}
}
puts "create_bd_addr_seg -range $p_seg_range -offset $p_address $sys_addr_cntrl_space $p_seg_name SEG_data_$p_name"
create_bd_addr_seg -range $p_seg_range \
-offset $p_address $sys_addr_cntrl_space \
$p_seg_name "SEG_data_${p_name}"
Expand All @@ -1157,6 +1166,22 @@ proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
}
}

## Create an AXI4 Lite memory mapped interface connection for register maps,
# instantiates an interconnect and reconfigure it at every process call.
#
# \param[p_address] - address offset of the IP register map
# \param[p_name] - name of the IP
# \param[p_intf_name] - name of the AXI MM Slave interface (optional)
#
proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {

if {$sys_zynq == -1} {ad_hpmx_interconnect "AXI" $p_address $p_name $p_intf_name}
elseif {$sys_zynq == 0} {ad_hpmx_interconnect "DP" $p_address $p_name $p_intf_name}
elseif {$sys_zynq == 1} {ad_hpmx_interconnect "GP0" $p_address $p_name $p_intf_name}
elseif {$sys_zynq == 2} {ad_hpmx_interconnect "HPM0_LPD" $p_address $p_name $p_intf_name}
elseif {$sys_zynq == 3} {ad_hpmx_interconnect "FPD" $p_address $p_name $p_intf_name}
}

## Connects an IP interrupt port to the system's interrupt controller interface.
#
# \param[p_ps_index] - interrupt index used in PSx based architecture
Expand Down
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