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Add support for AD408X on ZedBoard #1433
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So far, only about non-functional changes
V2: Cosmetics after review. |
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I also built the project and it looks good to me
Signed-off-by: PopPaul2021 <[email protected]>
Signed-off-by: PopPaul2021 <[email protected]>
Signed-off-by: PopPaul2021 <[email protected]>
The custom IP interface for AD408x has several operating capabilities: - single/dual lane data stream selection - bit-slip capability for synchronization - filter support Signed-off-by: PopPaul2021 <[email protected]>
Signed-off-by: PopPaul2021 <[email protected]>
The project instantiates: - the axi_ad408x interface IP - a DMA for the 20bit conversion data stream - the maximum clock for the axi_ad408x is 400MHz Signed-off-by: PopPaul2021 <[email protected]>
Signed-off-by: PopPaul2021 <[email protected]>
library/xilinx/common: Apply indentation patch on ad_serdes_in docs/projects/ad408x_fmc_evb: Update UG link position Signed-off-by: PopPaul2021 <[email protected]>
Signed-off-by: PopPaul2021 <[email protected]>
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V3: After fixing the critical warning and rebase. |
…ng the clock paths Signed-off-by: PopPaul2021 <[email protected]>
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PR Description
This PR adds the following:
PR Type
PR Checklist