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Add support for AD408X on ZedBoard #1433

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PR Description

This PR adds the following:

  • the ad_serdes_in module was modified to allow external reset
  • the ad_pack module was modified to allow MSB align
  • the up_adc_common exposes the up_adc_ddr_edgesel, up_adc_num_lanes and up_adc_sdr_ddr_n signals
  • AXI_AD408X IP
  • AXI_AD408X IP documentation
  • AD4080 project on ZedBoard
  • AD4080 project on ZedBoard documentation

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

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@IuliaCMoldovan IuliaCMoldovan left a comment

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So far, only about non-functional changes

docs/library/axi_ad408x/index.rst Show resolved Hide resolved
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projects/ad408x_fmc_evb/zed/system_project.tcl Outdated Show resolved Hide resolved
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@PopPaul2021
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V2: Cosmetics after review.

IuliaCMoldovan
IuliaCMoldovan previously approved these changes Aug 29, 2024
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I also built the project and it looks good to me

PopPaul2021 and others added 9 commits September 3, 2024 13:46
The custom IP interface for AD408x has several operating capabilities:
  - single/dual lane data stream selection
  - bit-slip capability for synchronization
  - filter support

Signed-off-by: PopPaul2021 <[email protected]>
The project instantiates:
  - the axi_ad408x interface IP
  - a DMA for the 20bit conversion data stream
  - the maximum clock for the axi_ad408x is 400MHz

Signed-off-by: PopPaul2021 <[email protected]>
library/xilinx/common: Apply indentation patch on ad_serdes_in
docs/projects/ad408x_fmc_evb: Update UG link position

Signed-off-by: PopPaul2021 <[email protected]>
@PopPaul2021
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V3: After fixing the critical warning and rebase.

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2 participants