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AD469x_fmc: Initial version for Coraz7s and DE-10Nano #1463
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Update Makefile |
Project should be renamed without "_fmc". I suggest "ad469x_evb" |
set spi_clk_ref_frequency 160 | ||
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# specify ADC resolution -- supported resolutions 16 bits | ||
set adc_resolution 16 | ||
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# specify ADC sampling rate in samples/seconds | ||
set adc_sampling_rate 1000000 |
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remove useless variables
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Removed all unused variables
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" | ||
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 | ||
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set sys_cstring "SPI_CLK_FREQ=$spi_clk_ref_frequency\ |
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cstring must contain build parameters
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Fixed!
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad469x_spi_sclk]; ## CK_IO13 | ||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports ad469x_spi_sdo]; ## CK_IO12 | ||
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports ad469x_spi_sdi]; ## CK_IO11 |
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remove pullups
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Done!
.dio_o(gpio_i[7:2]), | ||
.dio_p(led)); | ||
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assign gpio_i[31:8] = gpio_o[31:8]; |
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move higher next to other assigments
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done!
V1: Initial version for DE10-Nano |
de10nano has offload/trigger not connected and execution/sdi not connected |
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sync_bits #( | ||
.ASYNC_CLK(1) | ||
) i_sync_bits ( | ||
.in_bits (gpio_i[33]), |
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use ad469x_busy_alt_gp0 instead of gpio_i[33]
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Fixed!
.clk (spi_clk_s), | ||
.rst (1'b0), | ||
.signal_in (spi_trigger_ed), | ||
.signal_out (spi_trigger)); |
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spi_trigger not going anywhere
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Fixed!
.ad469x_spi_sdo_sdo (ad469x_spi_sdo), | ||
.ad469x_spi_resetn_reset_n (spi_resetn), | ||
.ad469x_spi_clk_clk (spi_clk_s), | ||
.ad469x_spi_cnv_if_pwm (ad469x_spi_cnv_s), |
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missing offload trigger input
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Fixed
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the de10nano project should also support build parameters, starting with SPI_4WIRE
this may be a good reference
https://github.com/analogdevicesinc/hdl/blob/main/projects/ad9081_fmca_ebz/a10soc/system_project.tcl
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Fixed
projects/ad469x_fmc/coraz7s/Makefile
Outdated
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cora project still failing
ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell ad469x_trigger_gen
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Fixed!
Done! |
V2: Fixed some findings |
Done! |
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add_instance ad469x_trigger_gen axi_pwm_gen | ||
set_instance_parameter_value ad469x_trigger_gen {N_PWMS} {1} | ||
set_instance_parameter_value ad469x_trigger_gen {PULSE_0_PERIOD} {$sampling_cycle} |
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remove variable
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Done!
Fixed! |
Signed-off-by: Liviu Adace <[email protected]>
Signed-off-by: Liviu Adace <[email protected]>
Signed-off-by: Liviu 'Ceshu' Adace <[email protected]>
Signed-off-by: Liviu 'Ceshu' Adace <[email protected]>
Signed-off-by: Liviu 'Ceshu' Adace <[email protected]>
Signed-off-by: Liviu 'Ceshu' Adace <[email protected]>
Signed-off-by: Liviu 'Ceshu' Adace <[email protected]>
RetriggerCI |
PR Description
Initial version for Coraz7s
PR Type
PR Checklist