Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

library: xilinx: common: ad_mmcm_drp: Add Versal family support #1507

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
Open

library: xilinx: common: ad_mmcm_drp: Add Versal family support #1507

wants to merge 1 commit into from

Conversation

bluncan
Copy link
Contributor

@bluncan bluncan commented Nov 6, 2024

PR Description

Adds mmcme5 instantiation for Versal boards inside ad_mmcm_drp. This allows us to use the axi_clkgen IP on Versal FPGAs as well.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@acostina acostina Awaiting requested review from acostina acostina is a code owner

@AndreiGrozav AndreiGrozav Awaiting requested review from AndreiGrozav AndreiGrozav is a code owner

@PopPaul2021 PopPaul2021 Awaiting requested review from PopPaul2021 PopPaul2021 is a code owner

@gastmaier gastmaier Awaiting requested review from gastmaier gastmaier is a code owner

@sarpadi sarpadi Awaiting requested review from sarpadi sarpadi is a code owner

At least 1 approving review is required to merge this pull request.

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
1 participant
@bluncan