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Fixes and add MODE 09 for AD9164 on ZCU102 #1511

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Fixes and add MODE 09 for AD9164 on ZCU102 #1511

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PopPaul2021
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PR Description

  • adding MODE 09 for AD9614 device
  • changing the source DMA DATA WIDTH to 128
  • changing the TX_LANE_INVERT from 0x0F to 0xF0
  • updating the xcvr parameters for 12.5GHz lane rate
  • cosmetics on the system_constr file

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@PopPaul2021
Fixes and add MODE 09 for AD9164 on ZCU102
4401fe8 
Changes made:

- adding MODE 09 for AD9614 device
- changing the source DMA DATA WIDTH to 128
- changing the TX_LANE_INVERT from 0x0F to 0xF0
- updating the xcvr parameters for 12.5GHz lane rate
- cosmetics on the system_constr file

Signed-off-by: PopPaul2021 <[email protected]>
@PopPaul2021
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Documentation update PR: #1510

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@IuliaCMoldovan IuliaCMoldovan Awaiting requested review from IuliaCMoldovan IuliaCMoldovan is a code owner

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@bluncan bluncan Awaiting requested review from bluncan bluncan is a code owner

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