hdl_2017_r1

Change log:

1. Supported tools version for this release are:
   • Vivado 2016.4*
   • Quartus 16.1
2. Major updates:
   • Updated License terms
   • Added ADI JESD204 Interface Framework and integrated it into all the JESD204 based projects
3. Library updates:
   • 1PPS receiver for axi_ad9361
   • avl_dacfifo for pl_ddrx offload (integrated to adrv9371/a10soc)
   • util_upack/util_rfifo - add valid signal turn around
4. Projects updates:
   • Rename pzsdr1 to adrv9364z7020
   • Rename pzsdr2 to adrv9361z7035
   • Several new porting:
     • adrv9371x to kcu105/zcu102
     • fmcomms2 to kcu105
     • daq1 to zed
     • daq3 to zcu102
   • Add adrv9379/zc706
   • Add util_dacfifo to daq3/a10gx
   • Add ad738x_fmc/zed

Note: The A10GX based projects may fail from time to time, as the synthesizer, router and mapper may not find a valid configuration. In case this happens, try regenerating the design with reduced address width for the ADC/DAC BRAM FIFOs.

*EXCEPTIONS: All the projects, that are using ZCU102 development platform, should be built with Vivado 2017.2, simply because Vivado 2016.4 does not support the production version of the FPGA (xczu9eg-ffvb1156-2-i).