ad7606x: Add testbench for AD7606x project's parallel interface

ad7606x/Makefile

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+####################################################################################
+####################################################################################
+## Copyright 2022 (c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# All test-bench dependencies except test programs
+SV_DEPS += ../common/sv/utils.svh
+SV_DEPS += ../common/sv/logger_pkg.sv
+SV_DEPS += ../common/sv/reg_accessor.sv
+SV_DEPS += ../common/sv/m_axis_sequencer.sv
+SV_DEPS += ../common/sv/s_axis_sequencer.sv
+SV_DEPS += ../common/sv/m_axi_sequencer.sv
+SV_DEPS += ../common/sv/s_axi_sequencer.sv
+SV_DEPS += ../common/sv/dmac_api.sv
+SV_DEPS += ../common/sv/adi_regmap_pkg.sv
+SV_DEPS += ../common/sv/adi_regmap_adc_pkg.sv
+SV_DEPS += ../common/sv/adi_regmap_common_pkg.sv
+SV_DEPS += ../common/sv/adi_regmap_dmac_pkg.sv
+SV_DEPS += ../common/sv/adi_regmap_pwm_gen_pkg.sv
+SV_DEPS += ../common/sv/dma_trans.sv
+SV_DEPS += ../common/sv/axi_dmac_pkg.sv
+SV_DEPS += system_tb.sv
+
+ENV_DEPS +=../../library/util_cdc/sync_bits.v
+ENV_DEPS +=../../library/common/ad_edge_detect.v
+ENV_DEPS += system_project.tcl
+ENV_DEPS += system_bd.tcl
+ENV_DEPS +=../scripts/adi_sim.tcl
+ENV_DEPS +=../scripts/run_sim.tcl
+
+LIB_DEPS += axi_ad7606x
+LIB_DEPS += axi_clkgen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_hdmi_tx
+LIB_DEPS += axi_i2s_adi
+LIB_DEPS += axi_pwm_gen
+LIB_DEPS += axi_spdif_tx
+LIB_DEPS += axi_sysid
+LIB_DEPS += sysid_rom
+LIB_DEPS += util_i2c_mixer
+LIB_DEPS += util_pack/util_cpack2 
+
+# default test program
+TP := test_program
+
+# config files should have the following format
+#  cfg_<param1>_<param2>.tcl
+CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
+#$(warning $(CFG_FILES))
+
+# List of tests and configuration combinations that has to be run
+# Format is:  <configuration>:<test name>
+TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
+
+#TESTS += cfg1:test_program_pi
+
+include ../scripts/project-sim.mk
+
+# usage :
+#
+# run specific test on a specific configuration in gui mode
+# 	make CFG=cfg_PI_7606B_CRC TST=test_program_pi MODE=gui
+#
+
+####################################################################################
+####################################################################################

ad7606x/README.md

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+Usage :
+
+Run all tests in batch mode:
+
+	make
+
+
+Run all tests in GUI mode:
+
+	make MODE=gui
+
+
+Run specific test on a specific configuration in gui mode:
+
+	make CFG=<name of cfg> TST=<name of test> MODE=gui
+
+
+Run all test from a configuration:
+
+	make <name of cfg>
+
+
+Where:
+
+ * <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
+ * <name of test> is a file from the tests directory without the tcl extension
+
+** NOTE
+ * cfg1 - AD7606B device selected;
+ * cfg2 - AD7606C-16 device selected;
+ * cfg3 - AD7606C-18 device selected;

ad7606x/cfgs/cfg1.tcl

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+global ad_project_params
+
+set ad_project_params(DEV_CONFIG) 0
+set ad_project_params(EXT_CLK) 0

ad7606x/cfgs/cfg2.tcl

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+global ad_project_params
+
+set ad_project_params(DEV_CONFIG) 1
+set ad_project_params(EXT_CLK) 0

ad7606x/cfgs/cfg3.tcl

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+global ad_project_params
+
+set ad_project_params(DEV_CONFIG) 2
+set ad_project_params(EXT_CLK) 0

ad7606x/system_bd.tcl

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+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+source ../../scripts/adi_env.tcl
+
+# system level parameters
+set DEV_CONFIG  $ad_project_params(DEV_CONFIG)
+set EXT_CLK $ad_project_params(EXT_CLK)
+
+global ad_project_params
+
+adi_project_files [list \
+	"../../library/common/ad_edge_detect.v" \
+	"../../library/util_cdc/sync_bits.v"]
+
+#
+#  Block design under test
+#
+
+source ../../projects/ad7606x_fmc/common/ad7606x_bd.tcl
+
+create_bd_port -dir O sys_clk
+
+ad_connect sys_clk sys_cpu_clk
+
+ad_ip_parameter axi_ad7606x CONFIG.DEV_CONFIG $DEV_CONFIG
+ad_ip_parameter axi_ad7606x CONFIG.EXT_CLK $EXT_CLK

ad7606x/system_project.tcl

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+source ../scripts/adi_sim.tcl
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+if {$argc < 1} {
+  puts "Expecting at least one argument that specifies the test configuration"
+  exit 1
+} else {
+  set cfg_file [lindex $argv 0]
+}
+
+# Read common config file
+source "cfgs/${cfg_file}"
+
+# Set the project name
+set project_name [file rootname $cfg_file]
+
+# Create the project
+adi_sim_project_xilinx $project_name "xc7z020clg484-1"
+
+# Add test files to the project
+adi_sim_project_files [list \
+ "../common/sv/utils.svh" \
+ "../common/sv/logger_pkg.sv" \
+ "../common/sv/reg_accessor.sv" \
+ "../common/sv/m_axis_sequencer.sv" \
+ "../common/sv/s_axis_sequencer.sv" \
+ "../common/sv/m_axi_sequencer.sv" \
+ "../common/sv/s_axi_sequencer.sv" \
+ "../common/sv/dmac_api.sv" \
+ "../common/sv/adi_regmap_pkg.sv" \
+ "../common/sv/adi_regmap_adc_pkg.sv" \
+ "../common/sv/adi_regmap_common_pkg.sv" \
+ "../common/sv/adi_regmap_dmac_pkg.sv" \
+ "../common/sv/adi_regmap_pwm_gen_pkg.sv" \
+ "../common/sv/dma_trans.sv" \
+ "../common/sv/axi_dmac_pkg.sv" \
+ "../common/sv/test_harness_env.sv" \
+ "tests/test_program.sv" \
+ "system_tb.sv"]
+
+#set a default test program
+adi_sim_add_define "TEST_PROGRAM=test_program"
+
+adi_sim_generate $project_name

ad7606x/system_tb.sv

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+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsabilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+`include "utils.svh"
+
+module system_tb();
+  wire [1:0]  adc_config_mode;
+  wire        rx_cnvst_n;
+  wire        rx_busy;
+  wire [15:0] rx_db_i;
+  wire [15:0] rx_db_o;
+  wire        rx_db_t;
+  wire        rx_rd_n;
+  wire        rx_wr_n;
+  wire        rx_cs_n;
+  wire        rx_first_data;
+  wire        rx_data_ready;
+  wire [3:0]  rx_ch_count;
+  wire        sys_clk;
+
+  reg         rx_cnvst_n_d = 1'b0;
+  reg         rx_rd_n_d = 1'b0;
+  reg [3:0]   rx_ch_count_d = 4'b0;
+
+  wire [4:0] num_chs;
+
+  parameter DEV_CONFIG = 0;
+  localparam NEG_EDGE = 1;
+
+  `TEST_PROGRAM test(
+    .adc_config_mode (adc_config_mode),
+    .rx_cnvst_n (rx_cnvst_n),
+    .rx_busy (rx_busy),
+    .rx_db_i (rx_db_i),
+    .rx_db_o (rx_db_o),
+    .rx_db_t (rx_db_t),
+    .rx_rd_n (rx_rd_n),
+    .rx_wr_n (rx_wr_n),
+    .rx_cs_n (rx_cs_n),
+    .rx_first_data (rx_first_data),
+    .rx_data_ready (rx_data_ready),
+    .rx_ch_count (rx_ch_count),
+    .sys_clk (sys_clk));
+
+  test_harness `TH (
+    .rx_cnvst_n (rx_cnvst_n),
+    .rx_busy (rx_busy),
+    .rx_db_i (rx_db_i),
+    .rx_db_o (rx_db_o),
+    .rx_db_t (rx_db_t),
+    .rx_rd_n (rx_rd_n),
+    .rx_wr_n (rx_wr_n),
+    .rx_cs_n (rx_cs_n),
+    .rx_first_data (rx_first_data),
+    .sys_clk (sys_clk));
+
+  always @(posedge sys_clk) begin
+    rx_cnvst_n_d <= rx_cnvst_n;
+    rx_rd_n_d <= rx_rd_n;
+  end
+
+  always @(posedge sys_clk) begin
+    if (~rx_rd_n & rx_rd_n_d) begin
+      rx_ch_count_d <= rx_ch_count_d  + 1;
+    end
+    if (rx_ch_count_d  == num_chs && (rx_rd_n & ~rx_rd_n_d)) begin // if ch_count is equal to number of channels to be read and is the rising_edge rd_n after last channel
+      rx_ch_count_d <= 0;
+    end
+  end
+
+  assign num_chs = (DEV_CONFIG == 0 || DEV_CONFIG == 1) ? ((adc_config_mode == 0 ? 8 : (adc_config_mode == 1 ? 9 : (adc_config_mode == 2 ? 16 : 17)))) : ((adc_config_mode == 0 || adc_config_mode == 2) ? 16 : 17);
+  assign rx_busy = (~rx_cnvst_n & rx_cnvst_n_d) ? 1'b1 : 1'b0;
+  assign rx_ch_count = rx_ch_count_d;
+  assign rx_data_ready = (~rx_rd_n & rx_rd_n_d) ? 1'b1 : 1'b0;
+  assign rx_first_data = (rx_ch_count_d == 1'b1) ? 1'b1 : 1'b0;
+
+endmodule