stm32/boards: Add definition for STM32H747I-DISCO.

Signed-off-by: Andrew Leech <[email protected]>
andrewleech · Sep 24, 2024 · 14a452a · 14a452a
1 parent 05d1693
commit 14a452a
Show file tree

Hide file tree

Showing 9 changed files with 476 additions and 156 deletions.
diff --git a/drivers/bus/softspi.c b/drivers/bus/softspi.c
@@ -35,6 +35,14 @@ int mp_soft_spi_ioctl(void *self_in, uint32_t cmd) {
             mp_hal_pin_output(self->sck);
             mp_hal_pin_output(self->mosi);
             mp_hal_pin_input(self->miso);
+            if (self->hold) {
+                mp_hal_pin_write(self->hold, 1);
+                mp_hal_pin_output(self->hold);
+            }
+            if (self->wp) {
+                mp_hal_pin_write(self->wp, 1);
+                mp_hal_pin_output(self->wp);
+            }
             break;
 
         case MP_SPI_IOCTL_DEINIT:

diff --git a/drivers/bus/spi.h b/drivers/bus/spi.h
@@ -46,6 +46,8 @@ typedef struct _mp_soft_spi_obj_t {
     mp_hal_pin_obj_t sck;
     mp_hal_pin_obj_t mosi;
     mp_hal_pin_obj_t miso;
+    mp_hal_pin_obj_t hold;
+    mp_hal_pin_obj_t wp;
 } mp_soft_spi_obj_t;
 
 extern const mp_spi_proto_t mp_soft_spi_proto;

diff --git a/drivers/memory/spiflash.c b/drivers/memory/spiflash.c
@@ -180,16 +180,18 @@ void mp_spiflash_init(mp_spiflash_t *self) {
     // Ensure SPI flash is out of sleep mode
     mp_spiflash_deepsleep_internal(self, 0);
 
-    #if defined(CHECK_DEVID)
     // Validate device id
     uint32_t devid;
     int ret = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3, &devid);
+    #if defined(CHECK_DEVID)
     if (ret != 0 || devid != CHECK_DEVID) {
         mp_spiflash_release_bus(self);
         return;
     }
+    #else
+    printf("DEVID: %d / %lx\n", ret, devid);
     #endif
-
+    
     if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
         // Set QE bit
         uint32_t sr = 0, cr = 0;

diff --git a/ports/stm32/boards/STM32H747I-DISCO/bdev.c b/ports/stm32/boards/STM32H747I-DISCO/bdev.c
@@ -31,7 +31,7 @@
 // Shared cache for first and second SPI block devices
 static mp_spiflash_cache_t spi_bdev_cache;
 #endif
-
+#if 0
 // First external SPI flash uses hardware QSPI interface
 const mp_spiflash_config_t spiflash_config = {
     .bus_kind = MP_SPIFLASH_BUS_QSPI,
@@ -41,5 +41,47 @@ const mp_spiflash_config_t spiflash_config = {
     .cache = &spi_bdev_cache,
     #endif
 };
+#endif
 
+#if 0
+static const mp_soft_qspi_obj_t soft_qspi_bus = {
+    .cs = pyb_pin_QSPI1_CS,
+    .clk = pyb_pin_QSPI1_CLK,
+    .io0 = pyb_pin_QSPI1_D0,
+    .io1 = pyb_pin_QSPI1_D1,
+    .io2 = pyb_pin_QSPI1_D2,
+    .io3 = pyb_pin_QSPI1_D3,
+};
+
+const mp_spiflash_config_t spiflash_config = {
+    .bus_kind = MP_SPIFLASH_BUS_QSPI,
+    .bus.u_qspi.data = (void *)&soft_qspi_bus,
+    .bus.u_qspi.proto = &mp_soft_qspi_proto,
+    #if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+    .cache = &spi_bdev_cache,
+    #endif
+};
+#endif
+
+#if 1
+static const mp_soft_spi_obj_t soft_spi_bus = {
+    .delay_half = MICROPY_HW_SOFTSPI_MIN_DELAY,
+    .polarity = 0,
+    .phase = 0,
+    .sck = pyb_pin_QSPI1_CLK,
+    .mosi = pyb_pin_QSPI1_D0,
+    .miso = pyb_pin_QSPI1_D1,
+    .hold = pyb_pin_QSPI1_D2,
+    .wp = pyb_pin_QSPI1_D3,
+};
+
+
+const mp_spiflash_config_t spiflash_config = {
+    .bus_kind = MP_SPIFLASH_BUS_SPI,
+    .bus.u_spi.cs = pyb_pin_QSPI1_CS,
+    .bus.u_spi.data = (void *)&soft_spi_bus,
+    .bus.u_spi.proto = &mp_soft_spi_proto,
+    .cache = &spi_bdev_cache,
+};
+#endif
 spi_bdev_t spi_bdev;
diff --git a/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h b/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h
@@ -107,8 +107,6 @@
 #define MICROPY_HW_RCC_QSPI_CLKSOURCE   (RCC_QSPICLKSOURCE_PLL2)
 
 // SMPS configuration
-// #define MICROPY_HW_PWR_SMPS_CONFIG      (PWR_LDO_SUPPLY)
-// #define MICROPY_HW_PWR_SMPS_CONFIG      (PWR_SMPS_1V8_SUPPLIES_LDO)
 #define MICROPY_HW_PWR_SMPS_CONFIG      (PWR_DIRECT_SMPS_SUPPLY)
 
 // Configure the analog switches for dual-pad pins.
@@ -125,17 +123,18 @@
 // #define MICROPY_HW_RTC_USE_CALOUT   (1)
 
 #if (MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE == 0)
-// QSPI flash #1 for storage
-#define MICROPY_HW_QSPI_PRESCALER           (2) // 100MHz
-#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (27)
-// Reserve 1MiB at the end for compatibility with alternate firmware that places WiFi blob here.
-#define MICROPY_HW_SPIFLASH_SIZE_BITS       (120 * 1024 * 1024)
+// QSPI flash #1 for storage (mt25ql512ab)
+// #define CHECK_DEVID                         (0xBA20)
+#define MICROPY_HW_QSPI_PRESCALER           (4) // 50MHz
+#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (29) // 64MB / 512Mbit
+#define MICROPY_HW_SPIFLASH_SIZE_BITS       (512 * 1024 * 1024)
 #define MICROPY_HW_QSPIFLASH_CS             (pyb_pin_QSPI1_CS)
 #define MICROPY_HW_QSPIFLASH_SCK            (pyb_pin_QSPI1_CLK)
 #define MICROPY_HW_QSPIFLASH_IO0            (pyb_pin_QSPI1_D0)
 #define MICROPY_HW_QSPIFLASH_IO1            (pyb_pin_QSPI1_D1)
 #define MICROPY_HW_QSPIFLASH_IO2            (pyb_pin_QSPI1_D2)
 #define MICROPY_HW_QSPIFLASH_IO3            (pyb_pin_QSPI1_D3)
+// Technically this is dual-flash chip/load but I'm not sure if that can be used here. Octal?
 
 // SPI flash #1, block device config
 extern const struct _mp_spiflash_config_t spiflash_config;
@@ -178,13 +177,13 @@ extern struct _spi_bdev_t spi_bdev;
 // #define MICROPY_HW_SPI1_MISO        (pin_B4)
 // #define MICROPY_HW_SPI1_MOSI        (pin_D7)
 
-// #define MICROPY_HW_SPI2_NSS         (pin_I0)
-// #define MICROPY_HW_SPI2_SCK         (pin_I1)
-// #define MICROPY_HW_SPI2_MISO        (pin_C2)
-// #define MICROPY_HW_SPI2_MOSI        (pin_C3)
+#define MICROPY_HW_SPI5_NSS         (pyb_pin_SPI5_NSS)
+#define MICROPY_HW_SPI5_SCK         (pyb_pin_SPI5_SCK)
+#define MICROPY_HW_SPI5_MISO        (pyb_pin_SPI5_MISO)
+#define MICROPY_HW_SPI5_MOSI        (pyb_pin_SPI5_MOSI)
 
 // USRSW is pulled low. Pressing the button makes the input go high.
-#define MICROPY_HW_USRSW_PIN        (pin_C13)
+#define MICROPY_HW_USRSW_PIN        (pyb_pin_WAKEUP)
 #define MICROPY_HW_USRSW_PULL       (GPIO_NOPULL)
 #define MICROPY_HW_USRSW_EXTI_MODE  (GPIO_MODE_IT_RISING)
 #define MICROPY_HW_USRSW_PRESSED    (1)
@@ -197,14 +196,18 @@ extern struct _spi_bdev_t spi_bdev;
 #define MICROPY_HW_LED_OFF(pin)     (mp_hal_pin_high(pin))
 
 // SD Card SDMMC
-// #define MICROPY_HW_SDCARD_SDMMC     (2)
-// #define MICROPY_HW_SDCARD_CK        (pin_D6)
-// #define MICROPY_HW_SDCARD_CMD       (pin_D7)
-// #define MICROPY_HW_SDCARD_D0        (pin_B14)
-// #define MICROPY_HW_SDCARD_D1        (pin_B15)
-// #define MICROPY_HW_SDCARD_D2        (pin_B3)
-// #define MICROPY_HW_SDCARD_D3        (pin_B4)
-// #define MICROPY_HW_SDCARD_MOUNT_AT_BOOT (0)
+#define MICROPY_HW_SDCARD_SDMMC     (1)
+#define MICROPY_HW_SDCARD_CK        (pyb_pin_SDCARD_CK)
+#define MICROPY_HW_SDCARD_CMD       (pyb_pin_SDCARD_CMD)
+#define MICROPY_HW_SDCARD_D0        (pyb_pin_SDCARD_D0)
+#define MICROPY_HW_SDCARD_D1        (pyb_pin_SDCARD_D1)
+#define MICROPY_HW_SDCARD_D2        (pyb_pin_SDCARD_D2)
+#define MICROPY_HW_SDCARD_D3        (pyb_pin_SDCARD_D3)
+#define MICROPY_HW_SDCARD_D4        (pyb_pin_SDCARD_D4)
+#define MICROPY_HW_SDCARD_D5        (pyb_pin_SDCARD_D5)
+#define MICROPY_HW_SDCARD_D6        (pyb_pin_SDCARD_D6)
+#define MICROPY_HW_SDCARD_D7        (pyb_pin_SDCARD_D7)
+#define MICROPY_HW_SDCARD_MOUNT_AT_BOOT (0)
 
 // FDCAN bus
 // #define MICROPY_HW_CAN1_NAME        "FDCAN1"
@@ -213,21 +216,23 @@ extern struct _spi_bdev_t spi_bdev;
 
 // USB config
 #define MICROPY_HW_USB_HS           (1)
+#define MICROPY_HW_USB_HS_ULPI3320  (1)
 #define MICROPY_HW_USB_HS_ULPI_NXT  (pyb_pin_USB_HS_NXT)
 #define MICROPY_HW_USB_HS_ULPI_STP  (pyb_pin_USB_HS_STP)
 #define MICROPY_HW_USB_HS_ULPI_DIR  (pyb_pin_USB_HS_DIR)
-#define MICROPY_HW_USB_HS_ULPI3320  (1)
 
 #define MICROPY_HW_USB_CDC_RX_DATA_SIZE     (1024)
 #define MICROPY_HW_USB_CDC_TX_DATA_SIZE     (1024)
 #define MICROPY_HW_USB_CDC_1200BPS_TOUCH    (1)
 #define GPIO_AF10_OTG_HS                    (GPIO_AF10_OTG2_HS)
 
 
-// SDRAM TODO update to: 8M x 32bit SDRAM is connected to SDRAM Bank1 of the STM32H747XIH6 FMC
-#define MICROPY_HW_SDRAM_SIZE               (256 * 1024 * 1024 / 8)  // 256 Mbit
+// SDRAM TODO update to: 32MB SDRAM is connected to SDRAM Bank1 of the STM32H747XIH6 FMC
+#define MICROPY_HW_SDRAM_SIZE               (32 * 8 * 1024 * 1024 / 8)  // 256 Mbit
 #define MICROPY_HW_SDRAM_STARTUP_TEST       (1)
-#define MICROPY_HW_SDRAM_TEST_FAIL_ON_ERROR (false)
+#define MICROPY_HW_SDRAM_TEST_FAIL_ON_ERROR (true)
+#define MICROPY_HEAP_START sdram_start()
+#define MICROPY_HEAP_END sdram_end()
 // #define MICROPY_HW_FMC_SWAP_BANKS           (1)
 
 // Timing configuration for 200MHz/2=100MHz (10ns)
@@ -264,68 +269,69 @@ extern struct _spi_bdev_t spi_bdev;
 #define MICROPY_HW_SDRAM_REFRESH_RATE       (64) // ms
 
 // SDRAM configuration
-#define MICROPY_HW_FMC_SDCKE1       (pin_H7)
-#define MICROPY_HW_FMC_SDNE1        (pin_H6)
-// #define MICROPY_HW_FMC_SDNBL0       (pin_E0)
-// #define MICROPY_HW_FMC_SDNBL1       (pin_E1)
-#define MICROPY_HW_FMC_SDCLK        (pin_G8)
-#define MICROPY_HW_FMC_SDNCAS       (pin_G15)
-#define MICROPY_HW_FMC_SDNRAS       (pin_F11)
-#define MICROPY_HW_FMC_SDNWE        (pin_H5)
-#define MICROPY_HW_FMC_BA0          (pin_G4)
-#define MICROPY_HW_FMC_BA1          (pin_G5)
-#define MICROPY_HW_FMC_NBL0         (pin_E0)
-#define MICROPY_HW_FMC_NBL1         (pin_E1)
-#define MICROPY_HW_FMC_A0           (pin_F0)
-#define MICROPY_HW_FMC_A1           (pin_F1)
-#define MICROPY_HW_FMC_A2           (pin_F2)
-#define MICROPY_HW_FMC_A3           (pin_F3)
-#define MICROPY_HW_FMC_A4           (pin_F4)
-#define MICROPY_HW_FMC_A5           (pin_F5)
-#define MICROPY_HW_FMC_A6           (pin_F12)
-#define MICROPY_HW_FMC_A7           (pin_F13)
-#define MICROPY_HW_FMC_A8           (pin_F14)
-#define MICROPY_HW_FMC_A9           (pin_F15)
-#define MICROPY_HW_FMC_A10          (pin_G0)
-#define MICROPY_HW_FMC_A11          (pin_G1)
-#define MICROPY_HW_FMC_A12          (pin_G2)
-// #define MICROPY_HW_FMC_A13          (pin_G)
-// #define MICROPY_HW_FMC_A14          (pin_G4)
-// #define MICROPY_HW_FMC_A15          (pin_G5)
-#define MICROPY_HW_FMC_D0           (pin_D14)
-#define MICROPY_HW_FMC_D1           (pin_D15)
-#define MICROPY_HW_FMC_D2           (pin_D0)
-#define MICROPY_HW_FMC_D3           (pin_D1)
-#define MICROPY_HW_FMC_D4           (pin_E7)
-#define MICROPY_HW_FMC_D5           (pin_E8)
-#define MICROPY_HW_FMC_D6           (pin_E9)
-#define MICROPY_HW_FMC_D7           (pin_E10)
-#define MICROPY_HW_FMC_D8           (pin_E11)
-#define MICROPY_HW_FMC_D9           (pin_E12)
-#define MICROPY_HW_FMC_D10          (pin_E13)
-#define MICROPY_HW_FMC_D11          (pin_E14)
-#define MICROPY_HW_FMC_D12          (pin_E15)
-#define MICROPY_HW_FMC_D13          (pin_D8)
-#define MICROPY_HW_FMC_D14          (pin_D9)
-#define MICROPY_HW_FMC_D15          (pin_D10)
-#define MICROPY_HW_FMC_D16          (pin_H8)
-#define MICROPY_HW_FMC_D17          (pin_H9)
-#define MICROPY_HW_FMC_D18          (pin_H10)
-#define MICROPY_HW_FMC_D19          (pin_H11)
-#define MICROPY_HW_FMC_D20          (pin_H12)
-#define MICROPY_HW_FMC_D21          (pin_H13)
-#define MICROPY_HW_FMC_D22          (pin_H14)
-#define MICROPY_HW_FMC_D23          (pin_H15)
-#define MICROPY_HW_FMC_D24          (pin_I0)
-#define MICROPY_HW_FMC_D25          (pin_I1)
-#define MICROPY_HW_FMC_D26          (pin_I2)
-#define MICROPY_HW_FMC_D27          (pin_I3)
-#define MICROPY_HW_FMC_D28          (pin_I6)
-#define MICROPY_HW_FMC_D29          (pin_I7)
-#define MICROPY_HW_FMC_D30          (pin_I9)
-#define MICROPY_HW_FMC_D31          (pin_I10)
+#define MICROPY_HW_FMC_SDCKE1       (pyb_pin_FMC_SDCKE1)
+#define MICROPY_HW_FMC_SDNE1        (pyb_pin_FMC_SDNE1)
+#define MICROPY_HW_FMC_SDCLK        (pyb_pin_FMC_SDCLK)
+#define MICROPY_HW_FMC_SDNCAS       (pyb_pin_FMC_SDNCAS)
+#define MICROPY_HW_FMC_SDNRAS       (pyb_pin_FMC_SDNRAS)
+#define MICROPY_HW_FMC_SDNWE        (pyb_pin_FMC_SDNWE)
+#define MICROPY_HW_FMC_BA0          (pyb_pin_FMC_BA0)
+#define MICROPY_HW_FMC_BA1          (pyb_pin_FMC_BA1)
+#define MICROPY_HW_FMC_NBL0         (pyb_pin_FMC_NBL0)
+#define MICROPY_HW_FMC_NBL1         (pyb_pin_FMC_NBL1)
+#define MICROPY_HW_FMC_NBL2         (pyb_pin_FMC_NBL2)
+#define MICROPY_HW_FMC_NBL3         (pyb_pin_FMC_NBL3)
+#define MICROPY_HW_FMC_A0           (pyb_pin_FMC_A0)
+#define MICROPY_HW_FMC_A1           (pyb_pin_FMC_A1)
+#define MICROPY_HW_FMC_A2           (pyb_pin_FMC_A2)
+#define MICROPY_HW_FMC_A3           (pyb_pin_FMC_A3)
+#define MICROPY_HW_FMC_A4           (pyb_pin_FMC_A4)
+#define MICROPY_HW_FMC_A5           (pyb_pin_FMC_A5)
+#define MICROPY_HW_FMC_A6           (pyb_pin_FMC_A6)
+#define MICROPY_HW_FMC_A7           (pyb_pin_FMC_A7)
+#define MICROPY_HW_FMC_A8           (pyb_pin_FMC_A8)
+#define MICROPY_HW_FMC_A9           (pyb_pin_FMC_A9)
+#define MICROPY_HW_FMC_A10          (pyb_pin_FMC_A10)
+#define MICROPY_HW_FMC_A11          (pyb_pin_FMC_A11)
+#define MICROPY_HW_FMC_A12          (pyb_pin_FMC_A12)
+#define MICROPY_HW_FMC_D0           (pyb_pin_FMC_D0)
+#define MICROPY_HW_FMC_D1           (pyb_pin_FMC_D1)
+#define MICROPY_HW_FMC_D2           (pyb_pin_FMC_D2)
+#define MICROPY_HW_FMC_D3           (pyb_pin_FMC_D3)
+#define MICROPY_HW_FMC_D4           (pyb_pin_FMC_D4)
+#define MICROPY_HW_FMC_D5           (pyb_pin_FMC_D5)
+#define MICROPY_HW_FMC_D6           (pyb_pin_FMC_D6)
+#define MICROPY_HW_FMC_D7           (pyb_pin_FMC_D7)
+#define MICROPY_HW_FMC_D8           (pyb_pin_FMC_D8)
+#define MICROPY_HW_FMC_D9           (pyb_pin_FMC_D9)
+#define MICROPY_HW_FMC_D10          (pyb_pin_FMC_D10)
+#define MICROPY_HW_FMC_D11          (pyb_pin_FMC_D11)
+#define MICROPY_HW_FMC_D12          (pyb_pin_FMC_D12)
+#define MICROPY_HW_FMC_D13          (pyb_pin_FMC_D13)
+#define MICROPY_HW_FMC_D14          (pyb_pin_FMC_D14)
+#define MICROPY_HW_FMC_D15          (pyb_pin_FMC_D15)
+#define MICROPY_HW_FMC_D16          (pyb_pin_FMC_D16)
+#define MICROPY_HW_FMC_D17          (pyb_pin_FMC_D17)
+#define MICROPY_HW_FMC_D18          (pyb_pin_FMC_D18)
+#define MICROPY_HW_FMC_D19          (pyb_pin_FMC_D19)
+#define MICROPY_HW_FMC_D20          (pyb_pin_FMC_D20)
+#define MICROPY_HW_FMC_D21          (pyb_pin_FMC_D21)
+#define MICROPY_HW_FMC_D22          (pyb_pin_FMC_D22)
+#define MICROPY_HW_FMC_D23          (pyb_pin_FMC_D23)
+#define MICROPY_HW_FMC_D24          (pyb_pin_FMC_D24)
+#define MICROPY_HW_FMC_D25          (pyb_pin_FMC_D25)
+#define MICROPY_HW_FMC_D26          (pyb_pin_FMC_D26)
+#define MICROPY_HW_FMC_D27          (pyb_pin_FMC_D27)
+#define MICROPY_HW_FMC_D28          (pyb_pin_FMC_D28)
+#define MICROPY_HW_FMC_D29          (pyb_pin_FMC_D29)
+#define MICROPY_HW_FMC_D30          (pyb_pin_FMC_D30)
+#define MICROPY_HW_FMC_D31          (pyb_pin_FMC_D31)
 
 // Ethernet via RMII
+// By default Ethernet is not enabled due to pin conflict
+// between ETH_MDC and SAI4_D1 of the MEMs digital microphone.
+// See UM2411 Rev 4 Ethernet section in board documentation for more
+// information on the hw jumper modification needed to enable it.
 #define MICROPY_HW_ETH_MDC          (pyb_pin_ETH_MDC)
 #define MICROPY_HW_ETH_MDIO         (pyb_pin_ETH_MDIO)
 #define MICROPY_HW_ETH_RMII_REF_CLK (pyb_pin_ETH_RMII_REF_CLK)

diff --git a/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.mk b/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.mk
@@ -7,7 +7,7 @@ USE_MBOOT ?= 0
 MCU_SERIES = h7
 CMSIS_MCU = STM32H747xx
 MICROPY_FLOAT_IMPL = double
-AF_FILE = boards/stm32h743_af.csv
+AF_FILE = boards/stm32h747_af.csv
 
 ifeq ($(USE_MBOOT),1)
 # When using Mboot all the text goes together after the filesystem