VEXIRSBConveter: Fix two places where regs do not have tags. (#253)

angr · Oct 29, 2024 · c6c4aa1 · c6c4aa1
1 parent a888ad8
commit c6c4aa1
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/ailment/converter_vex.py b/ailment/converter_vex.py
@@ -762,6 +762,9 @@ def convert(irsb, manager):  # pylint:disable=arguments-differ
                 ret_reg_offset,
                 manager.arch.bits,
                 reg_name=manager.arch.translate_register_name(ret_reg_offset, size=manager.arch.bits),
+                ins_addr=manager.ins_addr,
+                vex_block_addr=manager.block_addr,
+                vex_stmt_idx=DEFAULT_STATEMENT,
             )
             fp_ret_reg_offset = manager.arch.fp_ret_offset
             if fp_ret_reg_offset is not None and fp_ret_reg_offset != ret_expr:
@@ -771,6 +774,9 @@ def convert(irsb, manager):  # pylint:disable=arguments-differ
                     fp_ret_reg_offset,
                     manager.arch.bits,
                     reg_name=manager.arch.translate_register_name(fp_ret_reg_offset, size=manager.arch.bits),
+                    ins_addr=manager.ins_addr,
+                    vex_block_addr=manager.block_addr,
+                    vex_stmt_idx=DEFAULT_STATEMENT,
                 )
             else:
                 fp_ret_expr = None