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Update for Ghidra 11.2.1 #126

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Update for Ghidra 11.2.1 #126

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4 changes: 2 additions & 2 deletions docs/guide.rst
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Expand Up @@ -84,5 +84,5 @@ SLEIGH & P-Code References
--------------------------
Extensive documentation covering SLEIGH and P-Code is available online:

* `SLEIGH, P-Code Introduction <https://htmlpreview.github.io/?https://github.com/NationalSecurityAgency/ghidra/blob/Ghidra_11.1.2_build/GhidraDocs/languages/html/sleigh.html>`_
* `P-Code Reference Manual <https://htmlpreview.github.io/?https://github.com/NationalSecurityAgency/ghidra/blob/Ghidra_11.1.2_build/GhidraDocs/languages/html/pcoderef.html>`_
* `SLEIGH, P-Code Introduction <https://htmlpreview.github.io/?https://github.com/NationalSecurityAgency/ghidra/blob/Ghidra_11.2.1_build/GhidraDocs/languages/html/sleigh.html>`_
* `P-Code Reference Manual <https://htmlpreview.github.io/?https://github.com/NationalSecurityAgency/ghidra/blob/Ghidra_11.2.1_build/GhidraDocs/languages/html/pcoderef.html>`_
2 changes: 1 addition & 1 deletion docs/index.rst
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@@ -1,7 +1,7 @@
pypcode documentation
=====================
pypcode is a machine code disassembly and IR translation library for Python using the
excellent `SLEIGH <https://ghidra.re/courses/languages/html/sleigh.html>`__ library from the `Ghidra <https://ghidra-sre.org/>`__ framework (version 11.1.2).
excellent `SLEIGH <https://ghidra.re/courses/languages/html/sleigh.html>`__ library from the `Ghidra <https://ghidra-sre.org/>`__ framework (version 11.2.1).

This library was created primarily for use with `angr <http://angr.io>`__, which provides analyses and symbolic
execution of p-code.
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8 changes: 4 additions & 4 deletions pypcode/processors/68000/data/languages/68000.sinc
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Expand Up @@ -1529,9 +1529,9 @@ subdiv: regdr:regdq is regdq & regdr & divsz=1 & divsgn=1 {
:exg reg9an,regan is op=12 & reg9an & op8=1 & op37=9 & regan { local tmp = reg9an; reg9an=regan; regan=tmp; }
:exg reg9dn,regan is op=12 & reg9dn & op8=1 & op37=17 & regan { local tmp = reg9dn; reg9dn=regan; regan=tmp; }

:ext.w regdnw is op=4 & reg9dn=4 & op68=2 & op35=0 & regdnw { local tmp = regdnw:1; regdnw = sext(tmp); }
:ext.l regdn is op=4 & reg9dn=4 & op68=3 & op35=0 & regdn { local tmp = regdn:2; regdn = sext(tmp); }
:extb.l regdn is op=4 & reg9dn=4 & op68=7 & op35=0 & regdn { local tmp = regdn:1; regdn = sext(tmp); }
:ext.w regdnw is op=4 & reg9dn=4 & op68=2 & op35=0 & regdnw { local tmp = regdnw:1; regdnw = sext(tmp); resflags(regdnw); logflags(); }
:ext.l regdn is op=4 & reg9dn=4 & op68=3 & op35=0 & regdn { local tmp = regdn:2; regdn = sext(tmp); resflags(regdn); logflags(); }
:extb.l regdn is op=4 & reg9dn=4 & op68=7 & op35=0 & regdn { local tmp = regdn:1; regdn = sext(tmp); resflags(regdn); logflags(); }

@ifdef COLDFIRE
:halt is d16=0x4ac8 unimpl
Expand Down Expand Up @@ -2687,7 +2687,7 @@ m2fpC2: FPCR is FPCR & f12=1 { FPCR = *movemptr; movemptr = movemptr + 1
m2fpC2: is f12=0 { }
m2fpC1: m2fpC2" "FPSR is FPSR & f11=1 & m2fpC2 { FPSR = *movemptr; movemptr = movemptr + 12; }
m2fpC1: m2fpC2 is f11=0 & m2fpC2 { }
m2fpC0: { m2fpC1" "FPCR } is FPCR & f10=1 & m2fpC1 { FPCR = *movemptr; movemptr = movemptr + 12; }
m2fpC0: { m2fpC1" "FPIAR } is FPIAR & f10=1 & m2fpC1 { FPIAR = *movemptr; movemptr = movemptr + 12; }
m2fpC0: { m2fpC1 } is f10=0 & m2fpC1 { }

# Floating point control register to Memory
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7 changes: 7 additions & 0 deletions pypcode/processors/8051/data/languages/8051.opinion
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@@ -0,0 +1,7 @@
<opinions>
<constraint loader="Object Module Format (OMF-51)">
<constraint compilerSpecID="default">
<constraint primary="8051" processor="8051" endian="big" size="16" />
</constraint>
</constraint>
</opinions>
1 change: 1 addition & 0 deletions pypcode/processors/AARCH64/data/languages/AARCH64.ldefs
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Expand Up @@ -15,6 +15,7 @@
<compiler name="golang" spec="AARCH64_golang.cspec" id="golang"/>
<external_name tool="gnu" name="aarch64"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
<external_name tool="Golang.register.info.file" name="AARCH64_golang.register.info"/>
<external_name tool="qemu" name="qemu-aarch64"/>
</language>
<language processor="AARCH64"
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18 changes: 18 additions & 0 deletions pypcode/processors/AARCH64/data/languages/AARCH64_golang.cspec
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Expand Up @@ -281,8 +281,26 @@
<killedbycall>
<register name="x21"/>
<register name="x20"/>
<register name="x26"/>
<register name="x27"/>
</killedbycall>
<unaffected>
<register name="x0"/>
<register name="x1"/>
<register name="x2"/>
<register name="x3"/>
<register name="x4"/>
<register name="x5"/>
<register name="x6"/>
<register name="x7"/>
<register name="x8"/>
<register name="x9"/>
<register name="x10"/>
<register name="x11"/>
<register name="x12"/>
<register name="x13"/>
<register name="x14"/>
<register name="x15"/>
<register name="x16"/>
<register name="x17"/>
</unaffected>
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9 changes: 9 additions & 0 deletions pypcode/processors/AARCH64/data/languages/AARCH64_golang.register.info
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Expand Up @@ -6,5 +6,14 @@
<stack initialoffset="8" maxalign="8"/>
<current_goroutine register="x28"/>
<zero_register register="xzr" builtin="true"/>
<duffzero dest="x20" zero_arg="" zero_type=""/>
</register_info>
<register_info versions="V1_16">
<int_registers list=""/>
<float_registers list=""/>
<stack initialoffset="8" maxalign="8"/>
<current_goroutine register="x28"/>
<zero_register register="xzr" builtin="true"/>
<duffzero dest="x20" zero_arg="" zero_type=""/>
</register_info>
</golang>
8 changes: 7 additions & 1 deletion pypcode/processors/ARM/data/languages/ARM.dwarf
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Expand Up @@ -8,5 +8,11 @@
<register_mapping dwarf="17" ghidra="cpsr"/>
</register_mappings>
<call_frame_cfa value="0"/>
<use_formal_parameter_storage/>
<!--
In the past, this flag has been present in this file but was not correctly implemented in
the DWARF analyzer. The DWARF analyzer now respects this flag, and also has the
"Ignore Parameter Storage Info" toggle option to enable the same feature.
This flag is being left disabled to match recent DWARF analyzer behavior.
<use_formal_parameter_storage/>
-->
</dwarf>
8 changes: 7 additions & 1 deletion pypcode/processors/ARM/data/languages/ARMneon.dwarf
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Expand Up @@ -10,5 +10,11 @@
<register_mapping dwarf="64" ghidra="s0" auto_count="32"/> <!-- s0..s31 -->
</register_mappings>
<call_frame_cfa value="0"/>
<use_formal_parameter_storage/>
<!--
In the past, this flag has been present in this file but was not correctly implemented in
the DWARF analyzer. The DWARF analyzer now respects this flag, and also has the
"Ignore Parameter Storage Info" toggle option to enable the same feature.
This flag is being left disabled to match recent DWARF analyzer behavior.
<use_formal_parameter_storage/>
-->
</dwarf>
16 changes: 8 additions & 8 deletions pypcode/processors/ARM/data/languages/ARMneon.sinc
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Expand Up @@ -619,9 +619,9 @@ define pcodeop SHA1HashUpdateParity;
local op1 = Qd;
local op2 = Qn;
local op3 = Qm;
local op2lo:8 = op2(0);
local op1hi:8 = op1(8);
op2 = zext(op2lo << 64) | zext(op1hi);
local op2LowerHalf = zext(op2[0,64]) << 64;
local op1UpperHalf = zext(op1[64,64]);
op2 = op2LowerHalf | op1UpperHalf;
Qd = op1 ^ op2 ^ op3;
}

Expand All @@ -637,15 +637,15 @@ define pcodeop SHA1HashUpdateParity;
local X = Qd;
local Y = Qm;
local Tm = X ^ (Y >> 32);
local t0:4 = Tm(0);
local t1:4 = Tm(4);
local t2:4 = Tm(8);
local t3:4 = Tm(12);
local t0:4 = Tm[0, 32];
local t1:4 = Tm[32, 32];
local t2:4 = Tm[64, 32];
local t3:4 = Tm[96, 32];
local W0:4 = (t0 << 1 | t0 >> 31);
local W1:4 = (t1 << 1 | t1 >> 31);
local W2:4 = (t2 << 1 | t2 >> 31);
local W3:4 = (t3 << 1 | t3 >> 31) ^ (t0 << 2 | t0 >> 30);
Qd = zext(W3 << 96) | zext(W2 << 64) | zext(W1 << 32) | zext(W0);
Qd = (zext(W3) << 96) | (zext(W2) << 64) | (zext(W1) << 32) | zext(W0);
}

#######
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18 changes: 10 additions & 8 deletions pypcode/processors/ARM/data/languages/ARMv8.sinc
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Expand Up @@ -119,13 +119,14 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
:ldaexd^COND Rd,Rd2,[Rn]
is TMode=0 & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xe9f
{
local addr:4 = Rn;
build COND;
@if ENDIAN == "big"
Rd = *(Rn + 4);
Rd2 = *(Rn);
Rd = *(addr + 4);
Rd2 = *(addr);
@else # ENDIAN == "little"
Rd = *(Rn);
Rd2 = *(Rn + 4);
Rd = *(addr);
Rd2 = *(addr + 4);
@endif # ENDIAN == "little"
}

Expand All @@ -134,13 +135,14 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1111
& ItCond & thv_Rt & thv_Rt2 & thv_Rn
{
local addr:4 = thv_Rn;
build ItCond;
@if ENDIAN == "big"
thv_Rt = *(thv_Rn + 4);
thv_Rt2 = *(thv_Rn);
thv_Rt = *(addr + 4);
thv_Rt2 = *(addr);
@else # ENDIAN == "little"
thv_Rt = *(thv_Rn);
thv_Rt2 = *(thv_Rn + 4);
thv_Rt = *(addr);
thv_Rt2 = *(addr + 4);
@endif # ENDIAN == "little"
}

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40 changes: 40 additions & 0 deletions pypcode/processors/M16C/data/languages/M16C_60.cspec
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@@ -0,0 +1,40 @@
<?xml version="1.0" encoding="UTF-8"?>

<compiler_spec>
<global>
<range space="RAM"/>
</global>
<stackpointer register="SP" space="RAM"/>
<default_proto>
<prototype name="__stdcall" extrapop="unknown" stackshift="0">
<input>
<pentry maxsize="2" minsize="1">
<register name="R0"/>
</pentry>
<pentry maxsize="2" minsize="1">
<register name="R1"/>
</pentry>
<pentry maxsize="2" minsize="1">
<register name="R2"/>
</pentry>
<pentry maxsize="500" minsize="1" align="2"> <!-- TODO: Alignment should be 1, waiting for decompiler change -->
<addr space="stack" offset="0"/>
</pentry>
</input>
<output>
<pentry maxsize="2" minsize="1">
<register name="R3"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="A0"/>
<register name="A1"/>
<register name="INTB"/>
<register name="FB"/>
<register name="SB"/>
<register name="FLG"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>
20 changes: 20 additions & 0 deletions pypcode/processors/M16C/data/languages/M16C_60.ldefs
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<?xml version="1.0" encoding="UTF-8"?>

<language_definitions>
<!--
Version-1.1 12-Dec-2008 - complete rewrite of M16C_60.slaspec
-->
<language processor="M16C/60"
endian="little"
size="16"
variant="default"
version="1.1"
slafile="M16C_60.sla"
processorspec="M16C_60.pspec"
manualindexfile="../manuals/M16C_60.idx"
id="M16C/60:LE:16:default">
<description>Renesas M16C/60 16-Bit MicroComputer</description>
<compiler name="default" spec="M16C_60.cspec" id="default"/>
<external_name tool="gnu" name="m16c"/>
</language>
</language_definitions>
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