Resore riscv64le

angr · Nov 8, 2023 · 75b26dd · 75b26dd
1 parent f99e4a8
commit 75b26dd
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/pyvex/arches.py b/pyvex/arches.py
@@ -28,6 +28,7 @@ def __init__(self, name: str, bits: int, memory_endness: str, instruction_endnes
             "S390X": "VexArchS390X",
             "MIPS32": "VexArchMIPS32",
             "MIPS64": "VexArchMIPS64",
+            "RISCV64": "VexArchRISCV64",
         }[name]
         self.ip_offset = guest_offsets[
             (
@@ -42,6 +43,7 @@ def __init__(self, name: str, bits: int, memory_endness: str, instruction_endnes
                     "S390X": "ia",
                     "MIPS32": "pc",
                     "MIPS64": "pc",
+                    "RISCV64": "pc",
                 }[name],
             )
         ]
@@ -81,3 +83,4 @@ def get_register_offset(self, name: str) -> int:
 ARCH_MIPS32_LE = PyvexArch("MIPS32", 32, "Iend_LE")
 ARCH_MIPS64_BE = PyvexArch("MIPS64", 64, "Iend_BE")
 ARCH_MIPS64_LE = PyvexArch("MIPS64", 64, "Iend_LE")
+ARCH_RISCV64_LE = PyvexArch("RISCV64", 64, "Iend_LE", instruction_endness="Iend_LE")