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[WIP] Add ASIC Flow #2

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[WIP] Add ASIC Flow

[WIP] Add ASIC Flow #2

Triggered via pull request July 7, 2023 07:07
@lpawelczlpawelcz
synchronize #8
pcza/add-asic-env-sv
Status Failure
Total duration 29m 12s
Artifacts –

physical_design_flow.yml

on: pull_request
Build-Yosys-SystemVerilog  /  Build yosys-systemverilog
29m 2s
Build-Yosys-SystemVerilog / Build yosys-systemverilog
Run-Physical-Design-Flow  /  VeeR EL2 Physical Design Flow
Run-Physical-Design-Flow / VeeR EL2 Physical Design Flow
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1 error
Build-Yosys-SystemVerilog / Build yosys-systemverilog
Process completed with exit code 1.