[WIP] Add ASIC Flow #4
lpawelczphysical_design_flow.yml
on: pull_request
Build-Yosys-SystemVerilog
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Build yosys-systemverilog
31m 58s
Run-Physical-Design-Flow
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VeeR EL2 Physical Design Flow
7m 51s
Annotations
1 error
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Run-Physical-Design-Flow / VeeR EL2 Physical Design Flow
Process completed with exit code 2.
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Artifacts
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asic-flow-results
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1.18 MB |
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modified-sv-sources
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1.69 MB |
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