[WIP] Add ASIC Flow #6
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| name: VeeR-EL2 CI | |
| on: | |
| push: | |
| branches: ["main"] | |
| pull_request: | |
| workflow_dispatch: | |
| jobs: | |
| Build-Yosys-SystemVerilog: | |
| name: Build-Yosys-SystemVerilog | |
| uses: ./.github/workflows/build-yosys-systemverilog.yml | |
| Run-Physical-Design-Flow: | |
| name: Run-Physical-Design-Flow | |
| needs: [Build-Yosys-SystemVerilog] | |
| uses: ./.github/workflows/run-physical-design-flow.yml |