Added README.md for RISCV-DV and RISCOF tests

Signed-off-by: Maciej Kurc <[email protected]>

tools/riscof/README.md

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+# RISCOF for VeeR
+
+This folder stores configuration files and plugins needed for running [RISCOF](https://riscof.readthedocs.io/en/stable/) tests for VeeR.
+
+## Install prerequisities
+
+1. Setup Verilator
+
+Installation instructions are available in the [Verilator's User Guide](https://veripool.org/guide/latest/install.html). Make sure that the verilator executable is available (eg. by setting `PATH`).
+
+2. Setup Spike instruction set simulator (ISS)
+
+Follow the instruction from the [documentation](https://github.com/riscv-software-src/riscv-isa-sim#build-steps). After installation make sure that the spike binary is visible in the current path.
+
+## Setup
+
+1. Clone VeeR repository with submodules and set `RV_ROOT` to the repository path:
+
+```
+git clone --recurse-submodules [email protected]:chipsalliance/Cores-VeeR-EL2.git
+cd Cores-Veer-EL2
+export RV_ROOT=$(pwd)
+```
+
+2. Build verilated model of VeeR
+
+```
+${RV_ROOT}/configs/veer.config
+make -f ${RV_ROOT}/tools/Makefile verilator-build
+```
+
+3. Install RISCOF (in a Python virtual environment)
+
+```
+python3 -m venv env
+source env/bin/activate
+pip install git+https://github.com/riscv/riscof
+```
+
+4. Clone RISCOF official tests
+
+The RISCOF framework uses manually developed official test programs. These need to be installed:
+
+```
+mkdir work
+cd work
+riscof --verbose info arch-test --clone
+```
+
+There are tests that include RISC-V `Zicsr` extension which cannot be disabled. Since VeeR does not support this extension they need to be removed manually. This is a temporary workaround:
+```
+rm -rf riscv-arch-test/riscv-test-suite/rv32i_m/privilege/
+```
+
+5. Configure RISCOF
+
+Copy RISCOF configuration from VeeR repository to the working directory and build the test list:
+```
+cp ${RV_ROOT}/tools/riscof/config.ini ./
+cp -r ${RV_ROOT}/tools/riscof/spike ./
+cp -r ${RV_ROOT}/tools/riscof/veer ./
+riscof testlist --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env
+```
+
+6. Run RISCOF tests
+
+```
+riscof run --no-browser --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env
+```

tools/riscv-dv/README.md

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+# RISCV-DV for VeeR
+
+This folder contains utilities necessary for running [RISCV-DV](https://htmlpreview.github.io/?https://github.com/google/riscv-dv/blob/master/docs/build/singlehtml/index.html#) tests with VeeR as well as the master Makefile which facilitates the process.
+
+## Setup
+
+1. Clone VeeR repository with submodules and set `RV_ROOT` to the repository path:
+
+```
+git clone --recurse-submodules [email protected]:chipsalliance/Cores-VeeR-EL2.git
+cd Cores-Veer-EL2
+export RV_ROOT=$(pwd)
+```
+
+2. Setup the RISCV-DV framework
+
+The framework should be already cloned in `Cores-Veer-EL2/third_party/riscv-dv`. Install its dependencies, best using a Python virtual environment:
+
+```
+python3 -m venv env
+source env/bin/activate
+pip install -r ${RV_ROOT}/third_party/riscv-dv/requirements.txt
+```
+
+3. Setup Verilator
+
+Installation instructions are available in the [Verilator's User Guide](https://veripool.org/guide/latest/install.html). Make sure that the verilator executable is available (eg. by setting `PATH`).
+
+4. Setup instruction set simulator (ISS)
+
+RISCV-DV tests require a reference RISC-V program executor in a form of instruction set simulator. The RISCV-DV flow for VeeR supports three of them:
+
+   - Spike
+
+     Follow the instruction from the [documentation](https://github.com/riscv-software-src/riscv-isa-sim#build-steps). After installation make sure that the spike binary is visible in the current path.
+
+   - VeeR ISS (a.k.a. "whisper")
+
+     VeeR ISS (previously known as "whisper") is a simulator designed specifically for VeeR. Nontheless, it is still a valid RV32IMC instruction set simulator. To build and install VeeR ISS follow the instructions in its [documentation](https://github.com/chipsalliance/VeeR-ISS#compiling-whisper).
+
+   - Renode
+
+     [Renode](www.renode.io) is a full-fledged embedded system simulator developed at Antmicro. Its capabilities go beyond simulating a RISC-V core which does not prevent it from being used as a reference ISS in RISCV-DV.
+
+     Renode can be downloaded as a pre-built binary. Download the latest "linux-portable" release from https://github.com/renode/renode/releases and unpack it. For example:
+     ```
+     wget https://github.com/renode/renode/releases/download/v1.13.3/renode-1.13.3.linux-portable.tar.gz
+     tar -zxf renode-1.13.3.linux-portable.tar.gz
+     export PATH=${PATH}:`realpath renode_1.13.3_portable`
+     ```
+
+## Running tests
+
+To run the tests using the default setup do the following:
+```
+cd ${RV_ROOT}/tools/riscv-dv
+make run
+```
+
+To alter the settings set relevant variables. Either in environment or in the make call commandline:
+
+- `RISCV_DV_ISS`
+
+    Controls which ISS is used as the reference. Valid values are `spike`, `whisper` and `renode`.
+
+- `RISCV_DV_TEST`
+
+    RISCV-DV test name. Defaults to `riscv_arithmetic_basic_test`. A complete list of tests can be found in [RISCV-DV documentation](https://github.com/chipsalliance/riscv-dv/tree/master/pygen/pygen_src)
+
+- `RISCV_DV_ITER`
+
+    Test iteration count, default 1.
+
+- `RISCV_DV_BATCH`
+
+    Test batch count, default 1.
+
+- `RISCV_DV_SEED`
+
+    Random generator seed for RISCV-DV instruction randomizer
+
+- `COVERAGE`
+
+    Enables coverage data collection in Verilator. Valid values are `branch`, `toggle` and `functional`. More information about coverage in Verilator can be found in its [documentation](https://veripool.org/guide/latest/simulating.html#coverage-analysis).
+
+## CI
+
+RISCV-DV tests are run in GitHub actions CI. The workflow responsible for them can be found at `.github/workflows/test-riscv-dv.yml`