Added README.md for RISCV-DV and RISCOF tests

Signed-off-by: Maciej Kurc <[email protected]>

tools/riscv-dv/README.md

@@ -0,0 +1,61 @@
+# RISCV-DV for VeeR
+
+This folder contains utilities necessary for running [RISCV-DV](https://htmlpreview.github.io/?https://github.com/google/riscv-dv/blob/master/docs/build/singlehtml/index.html#) tests with VeeR as well as the master Makefile which facilitates the process.
+
+## Setup
+
+1. Clone VeeR repository with submodules and set `RV_ROOT` to the repository path:
+
+```
+git clone --recurse-submodules [email protected]:chipsalliance/Cores-VeeR-EL2.git
+cd Cores-Veer-EL2
+export RV_ROOT=$(pwd)
+```
+
+2. Setup the RISCV-DV framework
+
+The framework should be already cloned in `Cores-Veer-EL2/third_party/riscv-dv`. Install its dependencies, best using a Python virtual environment:
+
+```
+python3 -m venv env
+source env/bin/activate
+pip install -r ${RV_ROOT}/third_party/riscv-dv/requirements.txt
+```
+
+3. Setup Verilator
+
+Installation instructions are available in the [Verilator's User Guide](https://veripool.org/guide/latest/install.html). Make sure that the verilator executable is available (eg. by setting `PATH`).
+
+4. Setup instruction set simulator (ISS)
+
+RISCV-DV tests require a reference RISC-V program executor in a form of instruction set simulator. The RISCV-DV flow for VeeR supports three of them:
+
+- Sipke
+- VeeR ISS (a.k.a. "whisper")
+- Renode
+
+    1. Spike
+
+        spike
+
+    2. VeeR ISS
+
+        aaa
+
+    3. Renode
+
+        Renode
+
+## Running tests
+
+To run the tests using the default setup do the following:
+```
+cd ${RV_ROOT}/tools/riscv-dv
+make run
+```
+
+To alter the settings set relevant variables. Either in environment or in the make call commandline:
+
+- `RISCV_DV_ISS`
+
+    Controls which ISS is used as the reference. Valid values are `spike`, `whisper` and `renode`.