Reduce BUILD_DIR usage

Signed-off-by: Pawel Czarnecki <[email protected]>

docker_shell.sh

@@ -58,6 +58,8 @@ export STAGE_CONFIG_PREFIXED=$WORKSPACE_EXECROOT/$STAGE_CONFIG
 # Make bazel-bin writable
 chmod -R +w $WORKSPACE_EXECROOT/bazel-out/k8-fastbuild/bin
 
+export MAKEFILES=$FLOW_HOME/Makefile
+
 # Handle TERM signals
 # this option requires `supports-graceful-termination` tag in Bazel rule
 trap handle_sigterm SIGTERM
@@ -76,6 +78,7 @@ docker run --name "bazel-orfs-$uuid" --rm \
  -e XAUTHORITY=$XAUTH \
  -e BUILD_DIR=$WORKSPACE_EXECROOT \
  -e FLOW_HOME=$FLOW_HOME \
+ -e MAKEFILES=$MAKEFILES \
  -e DESIGN_CONFIG=$DESIGN_CONFIG_PREFIXED \
  -e STAGE_CONFIG=$STAGE_CONFIG_PREFIXED \
  -e MAKE_PATTERN=$MAKE_PATTERN_PREFIXED \
@@ -90,7 +93,7 @@ docker run --name "bazel-orfs-$uuid" --rm \
  bash -c \
  "set -ex
  . ./env.sh
- cd \$FLOW_HOME
+ cd \$BUILD_DIR
  $ARGUMENTS
  " &
 

memory-bazel.mk

@@ -1,7 +1,7 @@
 .PHONY: memory
 memory: $(RESULTS_DIR)/mem.json
-	python3 $(BUILD_DIR)/scripts/mem_dump.py $(RESULTS_DIR)/mem.json
+	python3 scripts/mem_dump.py $(RESULTS_DIR)/mem.json
 
 $(RESULTS_DIR)/mem.json: yosys-dependencies
 	mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
-	$(TIME_CMD) $(YOSYS_CMD) $(YOSYS_FLAGS) -c $(BUILD_DIR)/scripts/mem_dump.tcl 2>&1 | tee $(LOG_DIR)/1_0_mem.log
+	$(TIME_CMD) $(YOSYS_CMD) $(YOSYS_FLAGS) -c scripts/mem_dump.tcl 2>&1 | tee $(LOG_DIR)/1_0_mem.log

openroad.bzl

@@ -549,30 +549,26 @@ def build_openroad(
     macro_lef_targets, macro_lib_targets = x
     # macro_gds_targets = map(lambda m: "//:results/" + platform + "/%s/%s/6_final.gds" % (m, macro_variants.get(m, macro_variant)), macros)
 
-    io_constraints_args = ["IO_CONSTRAINTS=\\$$(BUILD_DIR)/$(location " + io_constraints + ")"] if io_constraints != None else []
+    io_constraints_args = ["IO_CONSTRAINTS=$(location " + io_constraints + ")"] if io_constraints != None else []
 
-    ADDITIONAL_LEFS = " ".join(map(lambda m: "\\$$(BUILD_DIR)/$(RULEDIR)/results/" + platform + "/%s/%s/%s.lef" % (m, macro_variants.get(m, macro_variant), m), macros))
-    ADDITIONAL_LIBS = " ".join(map(lambda m: "\\$$(BUILD_DIR)/$(RULEDIR)/results/" + platform + "/%s/%s/%s.lib" % (m, macro_variants.get(m, macro_variant), m), macros))
-    # ADDITIONAL_GDS_FILES = " ".join(map(lambda m: "\\$$(BUILD_DIR)/$(RULEDIR)/results/" + platform + "/%s/%s/6_final.gds" % (m, macro_variants.get(m, macro_variant)), macros))
+    ADDITIONAL_LEFS = " ".join(map(lambda m: "$(RULEDIR)/results/" + platform + "/%s/%s/%s.lef" % (m, macro_variants.get(m, macro_variant), m), macros))
+    ADDITIONAL_LIBS = " ".join(map(lambda m: "$(RULEDIR)/results/" + platform + "/%s/%s/%s.lib" % (m, macro_variants.get(m, macro_variant), m), macros))
+    # ADDITIONAL_GDS_FILES = " ".join(map(lambda m: "$(RULEDIR)/results/" + platform + "/%s/%s/6_final.gds" % (m, macro_variants.get(m, macro_variant)), macros))
 
     lefs_args = (["ADDITIONAL_LEFS=" + ADDITIONAL_LEFS] if len(macros) > 0 else [])
     libs_args = (["ADDITIONAL_LIBS=" + ADDITIONAL_LIBS] if len(macros) > 0 else [])
     # gds_args = (["ADDITIONAL_GDS_FILES=" + ADDITIONAL_GDS_FILES] if len(macros) > 0 else [])
 
-    extended_verilog_files = []
-    for file in verilog_files:
-        extended_verilog_files.append("\\$$(BUILD_DIR)/" + file)
-
     SDC_FILE_CLOCK_PERIOD = outs["clock_period"][0]
-    SDC_FILE = ["SDC_FILE=\\$$(BUILD_DIR)/$(location " + sdc_constraints + ")"] if sdc_constraints != None else []
+    SDC_FILE = ["SDC_FILE=$(location " + sdc_constraints + ")"] if sdc_constraints != None else []
 
     abstract_source = str(name_to_stage[mock_stage]) + "_" + mock_stage
 
     stage_args = init_stage_dict(all_stage_names, stage_args)
     stage_args["clock_period"] = SDC_FILE
     stage_args["synth_sdc"] = SDC_FILE
-    stage_args["synth"].append("VERILOG_FILES=" + " ".join(extended_verilog_files))
-    stage_args["synth"].append("SDC_FILE_CLOCK_PERIOD=\\$$(BUILD_DIR)/" + SDC_FILE_CLOCK_PERIOD)
+    stage_args["synth"].append("VERILOG_FILES=" + " ".join(verilog_files))
+    stage_args["synth"].append("SDC_FILE_CLOCK_PERIOD=" + SDC_FILE_CLOCK_PERIOD)
     stage_args["floorplan"] += SDC_FILE + (
         [] if len(macros) == 0 else [
             "CORE_MARGIN=4",