fix tests

Makefile

@@ -9,26 +9,25 @@ IMG=bunny.png
 TAG:=$(shell git describe --tags --abbrev=0)
 export TAG
 
-
 verilog:
-	$(MILL) vdma.runMain --mainClass $(DRIVER) $(CONFIG_FILE)
+	$(MILL) vdma.runMain --mainClass $(DRIVER) -- $(CONFIG_FILE)
 
 testsetup:
 	convert -resize $(SIZE_HALF)x$(SIZE_HALF) $(IMG) img0.rgba
 	convert -resize $(SIZE)x$(SIZE) $(IMG) img1.rgba
 
 testM2M: testsetup 
-	$(MILL) "Test / testOnly -t *$(TB)"
+	$(MILL) vdma.test.testOnly "*$(TB)"
 	convert -size $(SIZE)x$(SIZE) -depth 8 outAXI_AXIL_AXI.rgba outM2M.png
 
 testS2M: testsetup
-	$(MILL) "Test / testOnly -t *$(TB)"
+	$(MILL) vdma.test.testOnly "*$(TB)"
 	convert -size $(SIZE)x$(SIZE) -depth 8 outAXIS_AXIL_AXI.rgba outS2M.png
 
 test: testS2M testM2M
 
 testall: test
-	$(MILL) "test"
+	$(MILL) vdma.test
 
 clean:
 	$(MILL) clean

build.sc

@@ -8,7 +8,7 @@ object ivys {
   val ivyVersions = Map(
     "org.chipsalliance::chisel" -> "6.0.0",
     "org.chipsalliance:::chisel-plugin" -> "$chisel",
-    "edu.berkeley.cs::chiseltest" -> "6.0-SNAPSHOT",
+    "edu.berkeley.cs::chiseltest" -> "6.0.0",
     "edu.berkeley.cs::firrtl2" -> "$chiseltest",
     "org.scalatest::scalatest" -> "3.2.17",
     "org.scalacheck::scalacheck" -> "1.17.0",
@@ -126,7 +126,7 @@ trait InnerChiselTestModule
     extends CommonScalaModule
     with TestModule.ScalaTest {
   override def ivyDeps = super.ivyDeps() ++ Agg(
-    dep("chiseltest").excludeName("chisel", "chisel-plugin", "scalatest"),
+    dep("chiseltest"),//.excludeName("chisel", "chisel-plugin", "scalatest"),
     dep("scalatest"),
     dep("scalacheck")
   )

src/test/scala/DMAController/ComponentSpec.scala

@@ -24,7 +24,8 @@ import DMAController.DMAConfig._
 
 class ComponentSpec extends AnyFlatSpec with ChiselScalatestTester {
   val cfg = new DMAConfig("AXI_AXIL_AXI")
-  val testAnnotations = Seq(WriteVcdAnnotation)
+  // val testAnnotations = Seq(WriteVcdAnnotation)
+  val testAnnotations = Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)
 
   def testFastVDMAComponent[T <: Module](
       dutGen: => T,

src/test/scala/DMAController/ControllerSpec.scala

@@ -10,7 +10,7 @@ See the License for the specific language governing permissions and
 limitations under the License.
 
 SPDX-License-Identifier: Apache-2.0
-*/
+ */
 
 package DMAController
 
@@ -24,7 +24,8 @@ class ControllerSpec extends AnyFlatSpec with ChiselScalatestTester {
   val dmaConfigMM2MM = new DMAConfig("AXI_AXIL_AXI")
   it should "perform 2D MM2MM transfer with stride mem to mem" in {
     test(new DMATop(dmaConfigMM2MM))
-      .withAnnotations(Seq(WriteVcdAnnotation))
+      // .withAnnotations(Seq(WriteVcdAnnotation))
+      .withAnnotations(Seq(VerilatorBackendAnnotation))
       .runPeekPoke(dut =>
         new ImageTransfer(dut, new DMAFullMem(dut), dmaConfigMM2MM)
       )
@@ -33,7 +34,8 @@ class ControllerSpec extends AnyFlatSpec with ChiselScalatestTester {
   val dmaConfigS2MM = new DMAConfig("AXIS_AXIL_AXI")
   it should "perform 2D S2MM transfer with stride stream to mem" in {
     test(new DMATop(dmaConfigS2MM))
-      .withAnnotations(Seq(WriteVcdAnnotation))
+      // .withAnnotations(Seq(WriteVcdAnnotation))
+      .withAnnotations(Seq(VerilatorBackendAnnotation))
       .runPeekPoke(dut =>
         new ImageTransfer(dut, new DMAFullStream(dut), dmaConfigS2MM)
       )