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utils/i2c: Use helper variable for I2C access port
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Improves visibility, reduces code volume.

Internal-tag: [#69926]
Signed-off-by: Wiktoria Kuna <[email protected]>
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@wkkuna
wkkuna committed Dec 19, 2024
1 parent 84d675a commit fd2d59c
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Showing 2 changed files with 25 additions and 32 deletions.
55 changes: 24 additions & 31 deletions rowhammer_tester/scripts/utils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -584,6 +584,7 @@ def validate_keys(config_dict, valid_keys_set):


def i2c_read(wb, slave_addr, reg_addr, length, send_stop=True, reg_addr_size=1):
access_port = wb.regs.i2c_i2c_worker_fifos_access_port
w_state = wb.regs.i2c_i2c_worker_write_fifo_state.read()
w_depth = w_state & 0xFF
if length + 3 + reg_addr_size > w_depth:
Expand All @@ -594,19 +595,15 @@ def i2c_read(wb, slave_addr, reg_addr, length, send_stop=True, reg_addr_size=1):
raise ValueError(error_msg)
wb.regs.i2c_i2c_worker_i2c_ctrl.write(0)
wb.regs.i2c_worker.write(1)
wb.regs.i2c_i2c_worker_fifos_access_port.write(
access_port.write(
I2CQueueEntry(data=slave_addr << 1, ack=1, s_start=1, s_data=1, abort_on_nack=1).pack()
)
for i in range(reg_addr_size):
payload = (reg_addr >> (8 * i)) & 0xFF
wb.regs.i2c_i2c_worker_fifos_access_port.write(
I2CQueueEntry(data=payload, ack=1, s_data=1, abort_on_nack=1).pack()
)
access_port.write(I2CQueueEntry(data=payload, ack=1, s_data=1, abort_on_nack=1).pack())
if send_stop:
wb.regs.i2c_i2c_worker_fifos_access_port.write(
I2CQueueEntry(s_stop=1, abort_on_nack=1).pack()
)
wb.regs.i2c_i2c_worker_fifos_access_port.write(
access_port.write(I2CQueueEntry(s_stop=1, abort_on_nack=1).pack())
access_port.write(
I2CQueueEntry(data=slave_addr << 1 | 1, ack=1, s_start=1, s_data=1, abort_on_nack=1).pack()
)
discard_reads = 2 + reg_addr_size
Expand All @@ -616,7 +613,7 @@ def i2c_read(wb, slave_addr, reg_addr, length, send_stop=True, reg_addr_size=1):
sent = 0
for i in range(min(w_depth - w_entries, length)):
flag = i == (length - 1)
wb.regs.i2c_i2c_worker_fifos_access_port.write(
access_port.write(
I2CQueueEntry(
data=0xFF, ack=flag, s_data=1, s_stop=flag, s_idle=flag, abort_on_nack=not flag
).pack()
Expand All @@ -633,7 +630,7 @@ def i2c_read(wb, slave_addr, reg_addr, length, send_stop=True, reg_addr_size=1):
r_state = wb.regs.i2c_i2c_worker_read_fifo_state.read()
r_entries = r_state >> 8
for _ in range(r_entries):
resp = wb.regs.i2c_i2c_worker_fifos_access_port.read()
resp = access_port.read()

wb.regs.i2c_i2c_worker_i2c_ctrl.write(0x1) # Setup for FIFO clear
wb.regs.i2c_i2c_worker_start.write(1) # Clear FIFOs
Expand All @@ -646,7 +643,7 @@ def i2c_read(wb, slave_addr, reg_addr, length, send_stop=True, reg_addr_size=1):
w_entries = w_state >> 8
for _ in range(min(length - sent, w_depth - w_entries)):
flag = sent == (length - 1)
wb.regs.i2c_i2c_worker_fifos_access_port.write(
access_port.write(
I2CQueueEntry(
data=0xFF, ack=flag, s_data=1, s_stop=flag, s_idle=flag, abort_on_nack=not flag
).pack()
Expand All @@ -656,12 +653,12 @@ def i2c_read(wb, slave_addr, reg_addr, length, send_stop=True, reg_addr_size=1):
r_entries = r_state >> 8
i = 0
while i < r_entries and discard_reads > 0:
resp = wb.regs.i2c_i2c_worker_fifos_access_port.read()
resp = access_port.read()
discard_reads -= 1
i += 1
if sent == length:
for _ in range(r_entries - i):
resp = I2CQueueEntry().from_int(wb.regs.i2c_i2c_worker_fifos_access_port.read())
resp = I2CQueueEntry().from_int(access_port.read())
ret.append(resp.data)
time.sleep(0.001)
while not (wb.regs.i2c_i2c_worker_i2c_state.read() & 1):
Expand All @@ -671,6 +668,7 @@ def i2c_read(wb, slave_addr, reg_addr, length, send_stop=True, reg_addr_size=1):


def i2c_write(wb, slave_addr, reg_addr, data=None, reg_addr_size=1):
access_port = wb.regs.i2c_i2c_worker_fifos_access_port
if data is None:
data = list()
length = len(data)
Expand All @@ -684,22 +682,20 @@ def i2c_write(wb, slave_addr, reg_addr, data=None, reg_addr_size=1):
raise ValueError(error_msg)
wb.regs.i2c_i2c_worker_i2c_ctrl.write(0)
wb.regs.i2c_worker.write(1)
wb.regs.i2c_i2c_worker_fifos_access_port.write(
access_port.write(
I2CQueueEntry(data=slave_addr << 1, ack=1, s_start=1, s_data=1, abort_on_nack=1).pack()
)
for i in range(reg_addr_size):
payload = (reg_addr >> (8 * i)) & 0xFF
wb.regs.i2c_i2c_worker_fifos_access_port.write(
I2CQueueEntry(data=payload, ack=1, s_data=1, abort_on_nack=1).pack()
)
access_port.write(I2CQueueEntry(data=payload, ack=1, s_data=1, abort_on_nack=1).pack())
discard_reads = 1 + reg_addr_size
w_state = wb.regs.i2c_i2c_worker_write_fifo_state.read()
w_depth = w_state & 0xFF
w_entries = w_state >> 8
sent = 0
for _ in range(min(w_depth - w_entries, length)):
flag = sent == (length - 1)
wb.regs.i2c_i2c_worker_fifos_access_port.write(
access_port.write(
I2CQueueEntry(
data=data[sent],
ack=flag,
Expand All @@ -721,7 +717,7 @@ def i2c_write(wb, slave_addr, reg_addr, data=None, reg_addr_size=1):
r_state = wb.regs.i2c_i2c_worker_read_fifo_state.read()
r_entries = r_state >> 8
for _ in range(r_entries):
resp = wb.regs.i2c_i2c_worker_fifos_access_port.read()
resp = access_port.read()

wb.regs.i2c_i2c_worker_i2c_ctrl.write(0x1) # Setup for FIFO clear
wb.regs.i2c_i2c_worker_start.write(1) # Clear FIFOs
Expand All @@ -733,7 +729,7 @@ def i2c_write(wb, slave_addr, reg_addr, data=None, reg_addr_size=1):
w_entries = w_state >> 8
for _ in range(min(length - sent, w_depth - w_entries)):
flag = sent == (length - 1)
wb.regs.i2c_i2c_worker_fifos_access_port.write(
access_port.write(
I2CQueueEntry(
data=data[sent],
ack=flag,
Expand All @@ -747,7 +743,7 @@ def i2c_write(wb, slave_addr, reg_addr, data=None, reg_addr_size=1):
r_state = wb.regs.i2c_i2c_worker_read_fifo_state.read()
r_entries = r_state >> 8
for _ in range(r_entries):
resp = I2CQueueEntry().from_int(wb.regs.i2c_i2c_worker_fifos_access_port.read())
resp = I2CQueueEntry().from_int(access_port.read())
if discard_reads > 0:
discard_reads -= 1
continue
Expand All @@ -760,30 +756,27 @@ def i2c_write(wb, slave_addr, reg_addr, data=None, reg_addr_size=1):


def i2c_poll(wb, slave_addr):
wb.regs.i2c_i2c_worker_fifos_access_port.write(
access_port = wb.regs.i2c_i2c_worker_fifos_access_port
access_port.write(
I2CQueueEntry(data=slave_addr << 1, ack=1, s_start=1, s_data=1, s_stop=1, s_idle=1).pack()
)
wb.regs.i2c_worker.write(1)
wb.regs.i2c_i2c_worker_start.write(1)
wb.regs.i2c_worker.write(0)
while not (wb.regs.i2c_i2c_worker_i2c_state.read() & 1):
time.sleep(0.001)
resp = I2CQueueEntry().from_int(wb.regs.i2c_i2c_worker_fifos_access_port.read())
resp = I2CQueueEntry().from_int(access_port.read())
if resp.ack == 0:
return True
wb.regs.i2c_i2c_worker_fifos_access_port.write(
I2CQueueEntry(data=slave_addr << 1 | 1, ack=1, s_start=1, s_data=1).pack()
)
wb.regs.i2c_i2c_worker_fifos_access_port.write(
I2CQueueEntry(data=0xFF, ack=1, s_data=1, s_stop=1, s_idle=1).pack()
)
access_port.write(I2CQueueEntry(data=slave_addr << 1 | 1, ack=1, s_start=1, s_data=1).pack())
access_port.write(I2CQueueEntry(data=0xFF, ack=1, s_data=1, s_stop=1, s_idle=1).pack())
wb.regs.i2c_worker.write(1)
wb.regs.i2c_i2c_worker_start.write(1)
wb.regs.i2c_worker.write(0)
while not (wb.regs.i2c_i2c_worker_i2c_state.read() & 1):
time.sleep(0.001)
resp = I2CQueueEntry().from_int(wb.regs.i2c_i2c_worker_fifos_access_port.read())
wb.regs.i2c_i2c_worker_fifos_access_port.read()
resp = I2CQueueEntry().from_int(access_port.read())
access_port.read()
if resp.ack == 0:
return True
return False
Expand Down
2 changes: 1 addition & 1 deletion third_party/litex
Submodule litex updated 3 files
+103 −17 litex/soc/cores/i2c_worker.py
+1 −0 setup.py
+55 −73 test/test_bitbang.py

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