Update list of verilog-axi RTL files, fix logging

Internal-tag: [#57771] Signed-off-by: Rafal Kolucki <[email protected]>
antmicro · Apr 29, 2024 · 22ce47f · 22ce47f
1 parent 2d8a762
commit 22ce47f
Showing 1 changed file with 38 additions and 29 deletions.
diff --git a/scripts/pack_core.py b/scripts/pack_core.py
@@ -20,60 +20,68 @@
 click_r_file = click.Path(exists=True, file_okay=True, dir_okay=False, readable=True)
 
 AVAILABLE_LOG_LEVELS = ["NOTSET", "DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
-DEFAULT_LOG_LEVEL = "WARNING"
+DEFAULT_LOG_LEVEL = "INFO"
 
 
 cores = {
     "verilog-axi": {
         "root": "https://raw.githubusercontent.com/alexforencich/verilog-axi/master/rtl",
         "sources": [
             "arbiter.v",
-            "axi_adapter_rd.v",
             "axi_adapter.v",
+            "axi_adapter_rd.v",
             "axi_adapter_wr.v",
-            "axi_axil_adapter_rd.v",
             "axi_axil_adapter.v",
+            "axi_axil_adapter_rd.v",
             "axi_axil_adapter_wr.v",
+            # "axi_cdma.v",
             "axi_cdma_desc_mux.v",
-            "axi_crossbar_rd.v",
-            "axi_crossbar.v",
-            "axi_crossbar_wr.v",
-            "axi_dma_desc_mux.v",
+            # "axi_crossbar.v",  # unsupported parameter value
+            # "axi_crossbar_addr.v",
+            # "axi_crossbar_rd.v",  # unsupported parameter value
+            # "axi_crossbar_wr.v",  # unsupported parameter value
             "axi_dma.v",
-            "axi_dp_ram.v",
-            "axi_fifo_rd.v",
+            "axi_dma_desc_mux.v",
+            # "axi_dma_rd.v",
+            # "axi_dma_wr.v",
+            # "axi_dp_ram.v", # processing takes too much time
             "axi_fifo.v",
+            "axi_fifo_rd.v",
             "axi_fifo_wr.v",
-            "axil_adapter_rd.v",
+            # "axi_interconnect.v",
+            # "axi_ram.v", # processing takes too much time
+            "axi_ram_rd_if.v",
+            "axi_ram_wr_if.v",
+            "axi_ram_wr_rd_if.v",
+            "axi_register.v",
+            "axi_register_rd.v",
+            "axi_register_wr.v",
+            # "axi_vfifo.v",
+            "axi_vfifo_dec.v",
+            # "axi_vfifo_enc.v", # Unsup. expr. on dyn. range sel. on sig. `\seg_mem_rd_data'
+            "axi_vfifo_raw.v",
+            "axi_vfifo_raw_rd.v",
+            "axi_vfifo_raw_wr.v",
+            "axi_vfifo.v",
             "axil_adapter.v",
+            "axil_adapter_rd.v",
             "axil_adapter_wr.v",
-            "axil_cdc_rd.v",
             "axil_cdc.v",
+            "axil_cdc_rd.v",
             "axil_cdc_wr.v",
-            "axil_crossbar_rd.v",
             "axil_crossbar.v",
+            # "axil_crossbar_addr.v",
+            "axil_crossbar_rd.v",
             "axil_crossbar_wr.v",
-            "axil_dp_ram.v",
-            "axil_ram.v",
-            "axil_reg_if_rd.v",
+            # "axil_dp_ram.v", # processing takes too much time
+            # "axil_interconnect.v",
+            # "axil_ram.v", # processing takes too much time
             "axil_reg_if.v",
+            "axil_reg_if_rd.v",
             "axil_reg_if_wr.v",
-            "axil_register_rd.v",
             "axil_register.v",
+            "axil_register_rd.v",
             "axil_register_wr.v",
-            "axi_ram_rd_if.v",
-            "axi_ram.v",
-            "axi_ram_wr_if.v",
-            "axi_ram_wr_rd_if.v",
-            "axi_register_rd.v",
-            "axi_register.v",
-            "axi_register_wr.v",
-            "axi_vfifo_dec.v",
-            "axi_vfifo_enc.v",
-            "axi_vfifo_raw_rd.v",
-            "axi_vfifo_raw.v",
-            "axi_vfifo_raw_wr.v",
-            "axi_vfifo.v",
             "priority_encoder.v",
         ],
     }
@@ -121,6 +129,7 @@ def pack_core(log_level: str, name: str):
     core_files = []
 
     for file in core["sources"]:
+        logging.info(f"Fetching: {file}")
         core_files.append(HttpGetFile(f"{root_path}/{file}"))
 
     core_repo.add_files(VerilogFileHandler(core_files))