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Disallow Tuple[str] signal variant in an IP core description
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mszalkowski-ant committed Sep 26, 2024
1 parent dcaed24 commit ac208d4
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Showing 5 changed files with 48 additions and 67 deletions.
76 changes: 26 additions & 50 deletions tests/data/data_parse/axi_axil_adapter.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,8 @@ parameters:
CONVERT_NARROW_BURST: 0
signals:
in:
- - clk
- - rst
- clk
- rst
interfaces:
s_axi:
signals:
Expand All @@ -28,14 +28,12 @@ interfaces:
- s_axi_awburst
- 1
- 0
ARVALID:
- s_axi_arvalid
ARVALID: s_axi_arvalid
AWCACHE:
- s_axi_awcache
- 3
- 0
AWVALID:
- s_axi_awvalid
AWVALID: s_axi_awvalid
ARPROT:
- s_axi_arprot
- 2
Expand All @@ -44,12 +42,9 @@ interfaces:
- s_axi_awprot
- 2
- 0
BREADY:
- s_axi_bready
ARLOCK:
- s_axi_arlock
RREADY:
- s_axi_rready
BREADY: s_axi_bready
ARLOCK: s_axi_arlock
RREADY: s_axi_rready
ARSIZE:
- s_axi_arsize
- 2
Expand All @@ -66,10 +61,8 @@ interfaces:
- s_axi_awaddr
- (ADDR_WIDTH-1)
- 0
WVALID:
- s_axi_wvalid
AWLOCK:
- s_axi_awlock
WVALID: s_axi_wvalid
AWLOCK: s_axi_awlock
AWLEN:
- s_axi_awlen
- 7
Expand All @@ -78,8 +71,7 @@ interfaces:
- s_axi_wdata
- (AXI_DATA_WIDTH-1)
- 0
WLAST:
- s_axi_wlast
WLAST: s_axi_wlast
WSTRB:
- s_axi_wstrb
- (AXI_STRB_WIDTH-1)
Expand All @@ -97,18 +89,12 @@ interfaces:
- (AXI_ID_WIDTH-1)
- 0
out:
ARREADY:
- s_axi_arready
AWREADY:
- s_axi_awready
WREADY:
- s_axi_wready
RVALID:
- s_axi_rvalid
BVALID:
- s_axi_bvalid
RLAST:
- s_axi_rlast
ARREADY: s_axi_arready
AWREADY: s_axi_awready
WREADY: s_axi_wready
RVALID: s_axi_rvalid
BVALID: s_axi_bvalid
RLAST: s_axi_rlast
RDATA:
- s_axi_rdata
- (AXI_DATA_WIDTH-1)
Expand All @@ -134,16 +120,11 @@ interfaces:
m_axil:
signals:
in:
ARREADY:
- m_axil_arready
AWREADY:
- m_axil_awready
WREADY:
- m_axil_wready
RVALID:
- m_axil_rvalid
BVALID:
- m_axil_bvalid
ARREADY: m_axil_arready
AWREADY: m_axil_awready
WREADY: m_axil_wready
RVALID: m_axil_rvalid
BVALID: m_axil_bvalid
RDATA:
- m_axil_rdata
- (AXIL_DATA_WIDTH-1)
Expand All @@ -157,18 +138,14 @@ interfaces:
- 1
- 0
out:
ARVALID:
- m_axil_arvalid
AWVALID:
- m_axil_awvalid
ARVALID: m_axil_arvalid
AWVALID: m_axil_awvalid
AWPROT:
- m_axil_awprot
- 2
- 0
BREADY:
- m_axil_bready
WVALID:
- m_axil_wvalid
BREADY: m_axil_bready
WVALID: m_axil_wvalid
ARADDR:
- m_axil_araddr
- (ADDR_WIDTH-1)
Expand All @@ -177,8 +154,7 @@ interfaces:
- m_axil_awaddr
- (ADDR_WIDTH-1)
- 0
RREADY:
- m_axil_rready
RREADY: m_axil_rready
ARPROT:
- m_axil_arprot
- 2
Expand Down
2 changes: 2 additions & 0 deletions tests/data/data_parse/ip_core_invalid.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,8 @@ interfaces:
signals:
out:
ABC: []
non:
- nested
foobar: {}
barfoo:

Expand Down
2 changes: 1 addition & 1 deletion tests/data/data_parse/ip_core_valid.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ interfaces:
signals:
in:
- clk
- [rst]
- rst
- [leds, 10, 0]
- - btns
- 32
Expand Down
31 changes: 17 additions & 14 deletions tests/tests_parse/test_ip_desc.py
Original file line number Diff line number Diff line change
Expand Up @@ -45,11 +45,11 @@ def invalid_interface_compliance_core(self):
type: AXI4Stream
signals:
out:
TDATA: [p1]
TVALID: [p2]
TBUBU: [p3]
TDATA: p1
TVALID: p2
TBUBU: p3
in:
TREADY: [p4]"""
TREADY: p4"""
)

@pytest.fixture
Expand All @@ -63,11 +63,11 @@ def optional_missing_interface_compliance_core(self):
type: AXI4Stream
signals:
out:
TDATA: [p1]
TVALID: [p2]
TLAST: [p3]
TDATA: p1
TVALID: p2
TLAST: p3
in:
TREADY: [p4]"""
TREADY: p4"""
)

@pytest.fixture
Expand Down Expand Up @@ -159,21 +159,18 @@ def test_invalid_syntax(self, completely_invalid_core):
"in": {
1: [
{"_schema": ["Not a valid string."]},
{"_schema": ["Length must be 1."]},
{"_schema": ["Length must be 3."]},
{"_schema": ["Length must be 5."]},
],
2: [
{"_schema": ["Not a valid string."]},
{"_schema": ["Length must be 1."]},
{"_schema": ["Length must be 3."]},
{"_schema": ["Length must be 5."]},
],
3: [
{"_schema": ["Not a valid string."]},
{"_schema": ["Not a valid tuple."]},
{"_schema": ["Not a valid tuple."]},
{"_schema": ["Not a valid tuple."]},
],
},
"inout": ["Field may not be null."],
Expand Down Expand Up @@ -221,11 +218,17 @@ def test_invalid_syntax(self, completely_invalid_core):
"ABC": {
"value": [
{"_schema": ["Not a valid string."]},
{"_schema": ["Length must be 1."]},
{"_schema": ["Length must be 3."]},
{"_schema": ["Length must be 5."]},
]
}
},
"non": {
"value": [
{"_schema": ["Not a valid string."]},
{"_schema": ["Length must be 3."]},
{"_schema": ["Length must be 5."]},
]
},
},
"barfoo": ["Unknown field."],
"foobar": ["Unknown field."],
Expand Down Expand Up @@ -265,7 +268,7 @@ def test_valid_syntax(self, completely_valid_core, force_compliance):
"clk",
("btns", 32, 0, 15, 10),
("leds", 10, 0),
("rst",),
"rst",
("useless", 22, 10),
},
output=set(),
Expand Down
4 changes: 2 additions & 2 deletions topwrap/ip_desc.py
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@

_T = Union[str, int]

Signal = Union[str, Tuple[str], Tuple[str, _T, _T], Tuple[str, _T, _T, _T, _T]]
Signal = Union[str, Tuple[str, _T, _T], Tuple[str, _T, _T, _T, _T]]


@marshmallow_dataclass.dataclass(frozen=True)
Expand All @@ -50,7 +50,7 @@ def bounds(self) -> Tuple[_T, _T, _T, _T]:
def raw(self) -> Signal:
out = self.bounds
if out == (0, 0, 0, 0):
out = (self.name,)
out = self.name
elif out[:2] == out[2:]:
out = (self.name, *out[:2])
else:
Expand Down

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