Update revisions

Cores-VeeR-EL2 e2f31eb8019 Merge pull request #233 from KasiaMH/fix_out_ports_type
809bde65cfd Added reg to out ports to be valid left-hand side of a procedural assignment
caliptra-rtl 0e43b8e [UVM] Fixes for error prediction edge cases and some scoreboard race conditions (#586)

deps.json

@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "53888bcdf4ca3c07e5e715fb6386cb4cc643a61b"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "e0fd903581fdd8b11341b635f57335339873c09b"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "1852cfc2b19f5be98bf0a8d8019a6a8061736d05"}]}
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "53888bcdf4ca3c07e5e715fb6386cb4cc643a61b"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "e2f31eb8019c2e33f4b9b918b33b502be4727bbb"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "0e43b8e7011c1c8761e114bc949fcad6cf30538e"}]}