Update revisions

ibex fb49826c [dv] Cleanup some code in the compile_tb.py module
8e77bb39 [dv] Tweak ISS linker arg construction for Xcelium
caliptra-rtl 9f80a2b [TB] Fix coverage interface connections/parameters/coverpoints for AXI (#598)

deps.json

@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "f92d599e002ff0afb86edf3e19d18cb192f5ac20"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "0274d920df9badd796e4e65bf664aa6b907509ff"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "a2dc3a8974ef1e3230af82f5f17ddc489a24726f"}]}
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "fb49826c16aab4902f2bedb5456f2f9ec118a97a"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "0274d920df9badd796e4e65bf664aa6b907509ff"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "9f80a2bebb755233696929bf1da5ca0b90eba9a1"}]}