New QL LED driver #3
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| Original file line number | Diff line number | Diff line change |
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| # Copyright 2020 QuickLogic | ||
| # Licensed under the Apache License, Version 2.0 | ||
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| config EOS_S3_LED_BASIC | ||
| bool "EOS S3 basic LED driver" | ||
| help | ||
| Enable basic LED driver for QL S3. | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,58 @@ | ||
| /* | ||
| * ========================================================== | ||
| * | ||
| * Copyright (C) 2020 QuickLogic Corporation | ||
| * Licensed under the Apache License, Version 2.0 (the "License"); | ||
| * you may not use this file except in compliance with the License. | ||
| * You may obtain a copy of the License at | ||
| * http://www.apache.org/licenses/LICENSE-2.0 | ||
| * Unless required by applicable law or agreed to in writing, software | ||
| * distributed under the License is distributed on an "AS IS" BASIS, | ||
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| * | ||
| * File : eos_s3_led_config.h | ||
| * Purpose : This file contains the IO mux definitions for LEDs | ||
| * | ||
| * | ||
| * =========================================================== | ||
| * | ||
| */ | ||
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| #ifndef _INC_EOS_S3_LED_CONFIG | ||
| #define _INC_EOS_S3_LED_CONFIG | ||
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| #include <soc_pinmap.h> | ||
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| /* Set FPGA_LED0 to PAD18 */ | ||
| #define FPGA_LED0_PAD18 (PAD_CTRL_SEL_FPGA | PAD_OEN_NORMAL \ | ||
| | PAD_P_Z | PAD_SR_SLOW | PAD_E_4MA \ | ||
| | PAD_REN_DISABLE | PAD_SMT_DISABLE) | ||
| #define FPGA_LED0_PAD18_FBIO PAD18_FUNC_SEL_FBIO_18 | ||
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| /* Set FPGA_LED1 to PAD21 */ | ||
| #define FPGA_LED1_PAD21 (PAD_CTRL_SEL_FPGA | PAD_OEN_NORMAL \ | ||
| | PAD_P_Z | PAD_SR_SLOW | PAD_E_4MA \ | ||
| | PAD_REN_DISABLE | PAD_SMT_DISABLE) | ||
| #define FPGA_LED1_PAD21_FBIO PAD21_FUNC_SEL_FBIO_21 | ||
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| /* Set FPGA_LED2 to PAD22 */ | ||
| #define FPGA_LED2_PAD22 (PAD_CTRL_SEL_FPGA | PAD_OEN_NORMAL \ | ||
| | PAD_P_Z | PAD_SR_SLOW | PAD_E_4MA \ | ||
| | PAD_REN_DISABLE | PAD_SMT_DISABLE) | ||
| #define FPGA_LED2_PAD22_FBIO PAD22_FUNC_SEL_FBIO_22 | ||
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| #define FPGA_LED0_PAD 18 | ||
| #define FPGA_LED0_PAD_CFG FPGA_LED0_PAD18 | ||
| #define FPGA_LED0_FBIO_SEL FPGA_LED0_PAD18_FBIO | ||
| #define FPGA_LED1_PAD 21 | ||
| #define FPGA_LED1_PAD_CFG FPGA_LED1_PAD21 | ||
| #define FPGA_LED1_FBIO_SEL FPGA_LED1_PAD21_FBIO | ||
| #define FPGA_LED2_PAD 22 | ||
| #define FPGA_LED2_PAD_CFG FPGA_LED2_PAD22 | ||
| #define FPGA_LED2_FBIO_SEL FPGA_LED2_PAD22_FBIO | ||
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| #endif /* _INC_EOS_S3_LED_CONFIG */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,49 @@ | ||
| /* | ||
| * ========================================================== | ||
| * | ||
| * Copyright (C) 2020 QuickLogic Corporation | ||
| * Licensed under the Apache License, Version 2.0 (the "License"); | ||
| * you may not use this file except in compliance with the License. | ||
| * You may obtain a copy of the License at | ||
| * http://www.apache.org/licenses/LICENSE-2.0 | ||
| * Unless required by applicable law or agreed to in writing, software | ||
| * distributed under the License is distributed on an "AS IS" BASIS, | ||
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| * | ||
| * File : led_eos_s3_basic.c | ||
| * Purpose : This is the driver for basic LED controller IP. | ||
| * | ||
| * | ||
| * =========================================================== | ||
| * | ||
| */ | ||
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| #include <zephyr.h> | ||
| #include <soc.h> | ||
| #include <fpga_loader.h> | ||
| #include "eos_s3_led_basic_ip.h" | ||
| #include "eos_s3_led_config.h" | ||
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| static void config_ios(void) | ||
| { | ||
| eos_s3_io_mux(FPGA_LED0_PAD, FPGA_LED0_PAD_CFG); | ||
| eos_s3_io_mux(FPGA_LED1_PAD, FPGA_LED1_PAD_CFG); | ||
| eos_s3_io_mux(FPGA_LED2_PAD, FPGA_LED2_PAD_CFG); | ||
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| eos_s3_fbio_select(FPGA_LED0_PAD, FPGA_LED0_FBIO_SEL); | ||
| eos_s3_fbio_select(FPGA_LED1_PAD, FPGA_LED1_FBIO_SEL); | ||
| eos_s3_fbio_select(FPGA_LED2_PAD, FPGA_LED2_FBIO_SEL); | ||
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| } | ||
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| void program_fpga_ip(void) | ||
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There was a problem hiding this comment. I thought about loading bitstream inside other drivers and I came to conclusion that the best solution would be to introduce a new type of driver in Zephyr - FPGA manager. We should add |
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| { | ||
| /* Load bitstrem into FPGA */ | ||
| load_fpga(sizeof(axFPGABitStream), axFPGABitStream); | ||
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| /* Configure IOs */ | ||
| config_ios(); | ||
| } | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,18 @@ | ||
| # Copyright 2020 QuickLogic | ||
| # Licensed under the Apache License, Version 2.0 | ||
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| menuconfig EOS_S3_PWM | ||
| bool "EOS S3 LiteX PWM driver" | ||
| depends on HAS_DTS | ||
| help | ||
| Set if PWM IP generated with EOS S3 tools | ||
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| if EOS_S3_PWM | ||
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| config PWM_LITEX_INIT_PRIORITY | ||
| int "Init priority" | ||
| default 70 | ||
| help | ||
| PWM device driver initialization priority. | ||
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| endif # PWM_LITEX |
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Please do not change this selection, because
SOC_EOS_S3_FPGAconfiguration tells software if we want to initialize FPGA or not here. Without it clocks won't be set up.There was a problem hiding this comment.
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The main change I made in these commits is to program FPGA from M4 program itself, instead of doing it outside using Jlink. To enable this feature I have added EOS_S3_PROGRAM_FPGA. If someone wants to use the old way, one can enable SOC_EOS_S3_FPGA. I have not made any changes in this flow. Since all clocks are enabled with EOS_S3_PROGRAM_FPGA, other is not required. So EOS_S3_PROGRAM_FPGA and SOC_EOS_S3_FPGA are mutually exclusive.
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Does
eos_s3_pwm_ip.hcontainPWM_LITEX? If not you must add separate config entry like explained here.There was a problem hiding this comment.
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No it doesn't.
I'll add separate config entry.
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Added new configuration. However I understand from our H/W team that we are using litex pwm IP only, the bit stream is generated using symbi flow tools (with EOS S3 support). Our driver just loads the FPGA IP. It doesn't have full functions. For that I have to use pwm litex driver. So I have included that too.