Fix Rustdocs (amd64, nightly)" CI check (#5727)

* Remove unknown targets

* Fix parquet format lint

arrow-buffer/src/alloc/alignment.rs

@@ -80,15 +80,6 @@ pub const ALIGNMENT: usize = 1 << 5;
 #[cfg(target_arch = "sparc64")]
 pub const ALIGNMENT: usize = 1 << 6;
 
-// On ARM cache line sizes are fixed. both v6 and v7.
-// Need to add board specific or platform specific things later.
-/// Cache and allocation multiple alignment size
-#[cfg(target_arch = "thumbv6")]
-pub const ALIGNMENT: usize = 1 << 5;
-/// Cache and allocation multiple alignment size
-#[cfg(target_arch = "thumbv7")]
-pub const ALIGNMENT: usize = 1 << 5;
-
 // Operating Systems cache size determines this.
 // Currently no way to determine this without runtime inference.
 /// Cache and allocation multiple alignment size
@@ -107,9 +98,6 @@ pub const ALIGNMENT: usize = 1 << 5;
 // If you have smaller data with less padded functionality then use 32 with force option.
 // - https://devtalk.nvidia.com/default/topic/803600/variable-cache-line-width-/
 /// Cache and allocation multiple alignment size
-#[cfg(target_arch = "nvptx")]
-pub const ALIGNMENT: usize = 1 << 7;
-/// Cache and allocation multiple alignment size
 #[cfg(target_arch = "nvptx64")]
 pub const ALIGNMENT: usize = 1 << 7;
 

parquet/src/lib.rs

@@ -107,6 +107,8 @@ pub mod basic;
 /// Automatically generated code for reading parquet thrift definition.
 // see parquet/CONTRIBUTING.md for instructions on regenerating
 #[allow(clippy::derivable_impls, clippy::match_single_binding)]
+// Don't try and format auto generated code
+#[rustfmt::skip]
 pub mod format;
 
 #[macro_use]