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CI: Skip half of RISC-V, Xtensa and Simulator targets when a Complex PR is created / updated #14400

Merged
merged 1 commit into from
Oct 18, 2024

Commits on Oct 18, 2024

  1. CI: Skip half of RISC-V, Xtensa and Simulator targets when a Complex …

    …PR is created / updated
    
    When we submit or update a Complex PR that affects All Architectures (Arm, RISC-V, Xtensa, etc): CI Workflow shall run only half the jobs for RISC-V, Xtensa and Simulator:
    - `risc-v-01` to `03`
    - `xtensa-01`
    - `sim-01`
    
    When the Complex PR is Merged: CI Workflow will still run all jobs for RISC-V, Xtensa and Simulator:
    - `risc-v-01` to `06`
    - `xtensa-01` to `02`
    - `sim-01` to `02`
    
    Simple PRs with One Single Arch / Board will build the same way as before:
    - `risc-v-01` to `06`
    - `xtensa-01` to `02`
    - `sim-01` to `02`
    
    We hope to lower drastically our usage of GitHub Runners before the ASF Deadline, as explained here: apache#14376
    lupyuen committed Oct 18, 2024
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