sim/integration: clean up and fix all other tests

gateware/cal/cal.sv

@@ -124,10 +124,10 @@ always_ff @(posedge clk_256fs) begin
             end
             CAL_ST_OUT: begin
                 // Calibrated input samples are zeroed if jack disconnected.
-                out0  <= out[0][W-1:0];
-                out1  <= out[1][W-1:0];
-                out2  <= out[2][W-1:0];
-                out3  <= out[3][W-1:0];
+                out0  <= jack[0] ? out[0][W-1:0] : 0;
+                out1  <= jack[1] ? out[1][W-1:0] : 0;
+                out2  <= jack[2] ? out[2][W-1:0] : 0;
+                out3  <= jack[3] ? out[3][W-1:0] : 0;
                 out4  <= out[4][W-1:0];
                 out5  <= out[5][W-1:0];
                 out6  <= out[6][W-1:0];
@@ -142,11 +142,21 @@ always_ff @(posedge clk_256fs) begin
 end
 
 `ifdef COCOTB_SIM
+
+`ifdef UNIT_TEST
+initial begin
+  $dumpfile ("cal.vcd");
+  $dumpvars;
+  #1;
+end
+`endif
+
+// Shadow fake wires so we can look inside verilog arrays in vcd trace.
 generate
   genvar idx;
   for(idx = 0; idx < 8; idx = idx+1) begin: register
-    wire [31:0] tmp;
-    assign tmp = out[idx];
+    wire [31:0] out_dummy;
+    assign out_dummy = out[idx];
   end
 endgenerate
 `endif

gateware/drivers/ak4619.sv

@@ -123,4 +123,24 @@ always_ff @(posedge clk_256fs) begin
 end
 
 
+`ifdef COCOTB_SIM
+`ifdef UNIT_TEST
+initial begin
+  $dumpfile ("ak4619.vcd");
+  $dumpvars;
+  #1;
+end
+`endif
+
+// Shadow fake wires so we can look inside verilog arrays in vcd trace.
+generate
+  genvar idx;
+  for(idx = 0; idx < N_CHANNELS; idx = idx+1) begin: register
+    wire [W-1:0] adc_dummy;
+    assign adc_dummy = adc_words[idx];
+  end
+endgenerate
+
+`endif
+
 endmodule

gateware/drivers/pmod_i2c_master.sv

@@ -302,4 +302,14 @@ i2c_master #(.DW(4)) i2c_master_inst(
     .rst(rst)
 );
 
+`ifdef COCOTB_SIM
+`ifdef UNIT_TEST
+initial begin
+  $dumpfile ("pmod_i2c_master.vcd");
+  $dumpvars;
+  #1;
+end
+`endif
+`endif
+
 endmodule

gateware/eurorack_pmod.sv

@@ -118,10 +118,10 @@ ak4619 ak4619_instance (
     .sample_out1 (sample_adc1),
     .sample_out2 (sample_adc2),
     .sample_out3 (sample_adc3),
-    .sample_in0 (sample_dac0),
-    .sample_in1 (sample_dac1),
-    .sample_in2 (sample_dac2),
-    .sample_in3 (sample_dac3)
+    .sample_in0 (force_dac_output == 0 ? sample_dac0 : force_dac_output),
+    .sample_in1 (force_dac_output == 0 ? sample_dac1 : force_dac_output),
+    .sample_in2 (force_dac_output == 0 ? sample_dac2 : force_dac_output),
+    .sample_in3 (force_dac_output == 0 ? sample_dac3 : force_dac_output)
 );
 
 

gateware/sim/ak4619/Makefile

@@ -2,5 +2,6 @@ SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 VERILOG_SOURCES = ../../drivers/ak4619.sv
 MODULE = tb_ak4619
+COMPILE_ARGS += -DUNIT_TEST
 
 include $(shell cocotb-config --makefiles)/Makefile.sim

gateware/sim/cal/Makefile

@@ -2,5 +2,6 @@ SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 VERILOG_SOURCES = ../../cal/cal.sv
 MODULE = tb_cal
+COMPILE_ARGS += -DUNIT_TEST
 
 include $(shell cocotb-config --makefiles)/Makefile.sim

gateware/sim/cal/tb_cal.py

@@ -46,18 +46,23 @@ async def test_cal_00(dut):
 
 
     channel = 0
-    for cal_inx, cal_outx in [(dut.in0, dut.out0),
-                              (dut.in1, dut.out1),
-                              (dut.in2, dut.out2),
-                              (dut.in3, dut.out3),
-                              (dut.in4, dut.out4),
-                              (dut.in5, dut.out5),
-                              (dut.in6, dut.out6),
-                              (dut.in7, dut.out7)]:
+    all_ins_outs = [(dut.in0, dut.out0),
+                    (dut.in1, dut.out1),
+                    (dut.in2, dut.out2),
+                    (dut.in3, dut.out3),
+                    (dut.in4, dut.out4),
+                    (dut.in5, dut.out5),
+                    (dut.in6, dut.out6),
+                    (dut.in7, dut.out7)]
+    for cal_inx, cal_outx in all_ins_outs:
 
         for value in test_values:
             expect = ((value - cal_mem[channel*2]) *
                       cal_mem[channel*2 + 1]) >> 10
+            # Default all inputs to zero so we don't have undefined
+            # values everywhere else in the input array.
+            for i, o in all_ins_outs:
+                i.value = Force(0)
             cal_inx.value = Force(signed_to_twos_comp(value))
             if expect >  32000: expect = 32000
             if expect < -32000: expect = -32000

gateware/sim/integration/tb_integration.py

@@ -32,6 +32,8 @@ async def test_integration_00(dut):
     cocotb.start_soon(clk_256fs.start())
 
     dut.eurorack_pmod1.ak4619_instance.sdout1.value = 0
+    # Simulate all jacks connected so the cal core doesn't zero them
+    dut.eurorack_pmod1.jack.value = Force(0xFF)
 
     dut.sysmgr_instance.pll_lock.value = 0
     await RisingEdge(dut.clk_256fs)

gateware/sim/pmod_i2c_master/Makefile

@@ -3,5 +3,6 @@ TOPLEVEL_LANG ?= verilog
 VERILOG_SOURCES = ../../drivers/pmod_i2c_master.sv \
 				  ../../external/no2misc/rtl/i2c_master.v
 MODULE = tb_pmod_i2c_master
+COMPILE_ARGS += -DUNIT_TEST
 
 include $(shell cocotb-config --makefiles)/Makefile.sim