Skip to content

Commit

Permalink
gateware: switch clk_fs for strobe asserted once per sample (#61)
Browse files Browse the repository at this point in the history
* Instead of dividing `clk_256fs` by 256 to create `clk_fs`, switch to a strobe signal that is high once per sample. This makes it more obvious that the whole repository works in 1 clock domain.
* Tested all example DSP cores on ecpix5 and icebreaker.
  • Loading branch information
vk2seb authored Jun 12, 2024
1 parent b3123da commit c3cd979
Showing 33 changed files with 268 additions and 287 deletions.
2 changes: 1 addition & 1 deletion README.md
Original file line number Diff line number Diff line change
@@ -51,7 +51,7 @@ This repository contains a bunch of example DSP cores which are continuously bei
- `gateware/cores/clkdiv.sv` - Clock divider
- `gateware/cores/sampler.sv` - .wav sampler
- `gateware/cores/seqswitch.sv` - Sequential routing switch
- `gateware/cores/stereo_echo.sv` - Echo / decimating delay effect
- `gateware/cores/digital_echo.sv` - Echo / delay effect
- `gateware/cores/vca.sv` - VCA (voltage controlled amplifier)
- `gateware/cores/vco.sv` - VCO (voltage controlled oscillator)
- `gateware/cores/bitcrush.sv` - Bitcrusher
9 changes: 0 additions & 9 deletions gateware/boards/colorlight_i5/sysmgr.v
Original file line number Diff line number Diff line change
@@ -5,7 +5,6 @@ module sysmgr (
input wire clk_in,
input wire rst_in,
output wire clk_256fs,
output wire clk_fs,
output wire rst_out
);

@@ -15,12 +14,10 @@ wire pll_reset;
wire rst_i;

reg [7:0] rst_cnt;
reg [7:0] clkdiv;

assign pll_reset = rst_in;
assign rst_i = ~rst_cnt[7];
assign rst_out = rst_i;
assign clk_fs = clkdiv[7];

`ifndef VERILATOR_LINT_ONLY

@@ -75,10 +72,4 @@ always @(posedge clk_in)
else if (~rst_cnt[7])
rst_cnt <= rst_cnt + 1;

always @(posedge clk_256fs)
if (rst_i)
clkdiv <= 8'h00;
else
clkdiv <= clkdiv + 1;

endmodule // sysmgr
9 changes: 0 additions & 9 deletions gateware/boards/ecpix5/sysmgr.v
Original file line number Diff line number Diff line change
@@ -5,7 +5,6 @@ module sysmgr (
input wire clk_in,
input wire rst_in,
output wire clk_256fs,
output wire clk_fs,
output wire rst_out
);

@@ -15,12 +14,10 @@ wire pll_reset;
wire rst_i;

reg [7:0] rst_cnt;
reg [7:0] clkdiv;

assign rst_i = ~rst_cnt[7];
assign rst_out = rst_i;
assign pll_reset = rst_in;
assign clk_fs = clkdiv[7];

`ifndef VERILATOR_LINT_ONLY

@@ -71,10 +68,4 @@ always @(posedge clk_in)
else if (~rst_cnt[7])
rst_cnt <= rst_cnt + 1;

always @(posedge clk_256fs)
if (rst_i)
clkdiv <= 8'h00;
else
clkdiv <= clkdiv + 1;

endmodule // sysmgr
9 changes: 0 additions & 9 deletions gateware/boards/gatemate_evb/sysmgr.v
Original file line number Diff line number Diff line change
@@ -4,7 +4,6 @@ module sysmgr (
input wire clk_in,
input wire rst_in,
output wire clk_256fs,
output wire clk_fs,
output wire rst_out
);

@@ -14,12 +13,10 @@ wire pll_reset;
wire rst_i;

reg [7:0] rst_cnt;
reg [7:0] clkdiv;

assign pll_reset = rst_in;
assign rst_i = ~rst_cnt[7];
assign rst_out = rst_i;
assign clk_fs = clkdiv[7];

`ifndef VERILATOR_LINT_ONLY

@@ -46,10 +43,4 @@ always @(posedge clk_in)
else if (~rst_cnt[7])
rst_cnt <= rst_cnt + 1;

always @(posedge clk_256fs)
if (rst_i)
clkdiv <= 8'h00;
else
clkdiv <= clkdiv + 1;

endmodule // sysmgr
10 changes: 0 additions & 10 deletions gateware/boards/icebreaker/sysmgr.v
Original file line number Diff line number Diff line change
@@ -8,7 +8,6 @@ module sysmgr (
// but we leave all this PLL logic here as you might need to scale
// the clock down to 12m on different boards.
output wire clk_256fs,
output wire clk_fs,
output wire rst_out
);

@@ -22,12 +21,10 @@ module sysmgr (
wire rst_i;

reg [7:0] rst_cnt;
reg [7:0] clkdiv;

assign clk_256fs = clk_1x_i;
assign pll_reset_n = ~rst_in;
assign rst_i = rst_cnt[7];
assign clk_fs = clkdiv[7];

// PLL instance
`ifndef COCOTB_SIM
@@ -69,13 +66,6 @@ module sysmgr (
else if (rst_cnt[7])
rst_cnt <= rst_cnt + 1;

always @(posedge clk_256fs)
if (rst_i)
clkdiv <= 8'h00;
else
clkdiv <= clkdiv + 1;


`ifndef COCOTB_SIM
`ifndef VERILATOR_LINT_ONLY
SB_GB rst_gbuf_I (
9 changes: 0 additions & 9 deletions gateware/boards/pico_ice/sysmgr.v
Original file line number Diff line number Diff line change
@@ -3,18 +3,15 @@
module sysmgr (
input wire rst_in,
output wire clk_256fs,
output wire clk_fs,
output wire rst_out
);

wire clk_12m;
wire rst_i;

reg [7:0] rst_cnt = 8'h80;
reg [7:0] clkdiv;

assign clk_256fs = clk_12m;
assign clk_fs = clkdiv[7];
assign rst_i = rst_cnt[7];

`ifndef VERILATOR_LINT_ONLY
@@ -35,12 +32,6 @@ module sysmgr (
else if (rst_cnt[7])
rst_cnt <= rst_cnt + 1;

always @(posedge clk_256fs)
if (rst_i)
clkdiv <= 8'h00;
else
clkdiv <= clkdiv + 1;

`ifndef VERILATOR_LINT_ONLY
SB_GB rst_gbuf_I (
.USER_SIGNAL_TO_GLOBAL_BUFFER(rst_i),
9 changes: 2 additions & 7 deletions gateware/cal/cal.sv
Original file line number Diff line number Diff line change
@@ -26,7 +26,7 @@ module cal #(
)(
input rst,
input clk_256fs,
input clk_fs,
input strobe,
input [7:0] jack,
input signed [W-1:0] in0,
input signed [W-1:0] in1,
@@ -64,7 +64,6 @@ logic signed [W-1:0] cal_mem [0:(2*N_CHANNELS)-1];
logic signed [(2*W)-1:0] out [N_CHANNELS];
logic [2:0] ch;
logic [2:0] state;
logic l_clk_fs;

// Calibration memory for 8 channels stored as
// 2 bytes shift, 2 bytes multiply * 8 channels.
@@ -73,7 +72,6 @@ initial $readmemh(CAL_MEM_FILE, cal_mem);
always_ff @(posedge clk_256fs) begin

if (rst) begin
l_clk_fs <= 0;
ch <= 0;
state <= CAL_ST_LATCH;
out[0] <= 0;
@@ -86,10 +84,7 @@ always_ff @(posedge clk_256fs) begin
out[7] <= 0;
end else begin

l_clk_fs <= clk_fs;

// On rising clk_fs.
if (clk_fs && (l_clk_fs != clk_fs)) begin
if (strobe) begin
state <= CAL_ST_LATCH;
ch <= 0;
end else begin
16 changes: 10 additions & 6 deletions gateware/cores/bitcrush.sv
Original file line number Diff line number Diff line change
@@ -14,7 +14,7 @@ module bitcrush #(
)(
input rst,
input clk,
input sample_clk,
input strobe,
input signed [W-1:0] sample_in0,
input signed [W-1:0] sample_in1,
input signed [W-1:0] sample_in2,
@@ -27,6 +27,7 @@ module bitcrush #(
);

logic signed [W-1:0] mask;
logic signed [W-1:0] out0;
logic signed [W-1:0] out1;
logic signed [W-1:0] out2;
logic signed [W-1:0] out3;
@@ -43,13 +44,16 @@ assign mask = (sample_in0 > 4*5000) ? 16'b1111111111111111 :
(sample_in0 > 4* 500) ? 16'b1110000000000000 :
16'b1100000000000000;

always_ff @(posedge sample_clk) begin
out1 <= sample_in1 & mask;
out2 <= sample_in2 & mask;
out3 <= sample_in3 & mask;
always_ff @(posedge clk) begin
if (strobe) begin
out0 <= sample_in0;
out1 <= sample_in1 & mask;
out2 <= sample_in2 & mask;
out3 <= sample_in3 & mask;
end
end

assign sample_out0 = sample_in0;
assign sample_out0 = out0;
assign sample_out1 = out1;
assign sample_out2 = out2;
assign sample_out3 = out3;
18 changes: 10 additions & 8 deletions gateware/cores/clkdiv.sv
Original file line number Diff line number Diff line change
@@ -19,7 +19,7 @@ module clkdiv #(
)(
input rst,
input clk,
input sample_clk,
input strobe,
input signed [W-1:0] sample_in0,
input signed [W-1:0] sample_in1,
input signed [W-1:0] sample_in2,
@@ -46,13 +46,15 @@ localparam OUT_LO = `FROM_MV(0);
logic last_state_hi = 1'b0;
logic [3:0] div = 0;

always_ff @(posedge sample_clk) begin
if (sample_in0 > SCHMITT_HI && !last_state_hi) begin
last_state_hi <= 1'b1;
// Increment count on every rising edge.
div <= div + 1;
end else if (sample_in0 < SCHMITT_LO && last_state_hi) begin
last_state_hi <= 1'b0;
always_ff @(posedge clk) begin
if (strobe) begin
if (sample_in0 > SCHMITT_HI && !last_state_hi) begin
last_state_hi <= 1'b1;
// Increment count on every rising edge.
div <= div + 1;
end else if (sample_in0 < SCHMITT_LO && last_state_hi) begin
last_state_hi <= 1'b0;
end
end
end

32 changes: 6 additions & 26 deletions gateware/cores/stereo_echo.sv → gateware/cores/digital_echo.sv
Original file line number Diff line number Diff line change
@@ -1,27 +1,20 @@
// Dual digital echo effect.
// Digital echo effect.
//
// Given input audio on input 0 / 1, apply a digital echo effect.
//
// Mapping:
// - Input 0: Audio input 0
// - Input 1: Audio input 1
// - Output 0: Audio input 0 (mirrored)
// - Output 1: Audio input 0 (echo)
// - Output 2: Audio input 1 (mirrored)
// - Output 3: Audio input 1 (echo)

module stereo_echo #(
module digital_echo #(
parameter W = 16,
// Length of the echo buffers in samples.
parameter ECHO_LEN = 2048,
// Decimate samples - this allows you to get long echo times
// without using all the BRAM. Effectively you end up with:
// ECHO_LEN (effective) = ECHO_LEN * (2 << DECIMATE)
parameter DECIMATE = 2
parameter ECHO_LEN = 4096
)(
input rst,
input clk,
input sample_clk,
input strobe,
input signed [W-1:0] sample_in0,
input signed [W-1:0] sample_in1,
input signed [W-1:0] sample_in2,
@@ -33,26 +26,13 @@ module stereo_echo #(
input [7:0] jack
);

logic [15:0] decimate = 0;
logic decimate_clk = decimate[DECIMATE];

always_ff @(posedge sample_clk) begin
decimate <= decimate + 1;
end

echo #(W, ECHO_LEN) echo0(
.sample_clk(decimate_clk),
.clk(clk),
.strobe(strobe),
.sample_in(sample_in0),
.sample_out(sample_out1)
);

echo #(W, ECHO_LEN) echo1(
.sample_clk(decimate_clk),
.sample_in(sample_in1),
.sample_out(sample_out3)
);

assign sample_out0 = sample_in0;
assign sample_out2 = sample_in1;

endmodule
4 changes: 2 additions & 2 deletions gateware/cores/filter.sv
Original file line number Diff line number Diff line change
@@ -13,7 +13,7 @@ module filter #(
)(
input rst,
input clk,
input sample_clk,
input strobe,
input signed [W-1:0] sample_in0,
input signed [W-1:0] sample_in1,
input signed [W-1:0] sample_in2,
@@ -28,7 +28,7 @@ module filter #(
karlsen_lpf_pipelined #(.W(W)) lpf_inst(
.rst(rst),
.clk(clk),
.sample_clk(sample_clk),
.strobe(strobe),
.sample_in(sample_in0),
.sample_out(sample_out0),
.g(sample_in1),
2 changes: 1 addition & 1 deletion gateware/cores/mirror.sv
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@ module mirror #(
)(
input rst,
input clk,
input sample_clk,
input strobe,
input signed [W-1:0] sample_in0,
input signed [W-1:0] sample_in1,
input signed [W-1:0] sample_in2,
5 changes: 3 additions & 2 deletions gateware/cores/pitch_shift.sv
Original file line number Diff line number Diff line change
@@ -14,7 +14,7 @@ module pitch_shift #(
)(
input rst,
input clk,
input sample_clk,
input strobe,
input signed [W-1:0] sample_in0,
input signed [W-1:0] sample_in1,
input signed [W-1:0] sample_in2,
@@ -29,7 +29,8 @@ module pitch_shift #(
transpose #(
.W(W)
) transpose_instance (
.sample_clk(sample_clk),
.clk,
.strobe,
.pitch(sample_in1),
.sample_in(sample_in0),
.sample_out(sample_out1)
Loading

0 comments on commit c3cd979

Please sign in to comment.