gateware: reapply (#33, #36), fixing timing bug in ak4619 driver #41
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* Change default sample rate from ~96khz to ~48kHz and BICK from 12MHz -> 6MHz which improves stability a bit with long cables from FPGA/PMOD. There is no audible difference and the noise performance is a bit better. * Clean up clocking architecture so we can select any sample rate from 8kHz to 48kHz, removing fixed 12MHz assumptions everywhere. * Rewrite AK4619 driver to collapse most of the logic into one posedge block on clk_256fs. * Some other minor fixes so that this repository plays better with LiteX (splitting out the wavetable osc as its own module, bubbling up .hex config paths). * Compress ECP5 bitstreams so they upload faster TESTED on all supported platforms
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Previously after #33 some of the examples stopped working in a way that was PnR dependent, so I reverted them. In the meantime I found a timing bug in those PRs in the ak4619vn driver where the clk_fs and internal clkdiv were not synchronized correctly. This PR includes those PRs which were reverted plus this timing fix which seems to stabilize all of the example cores.