Translate uart irq number on all arm platforms

.github/workflows/build.yml

@@ -132,7 +132,7 @@ jobs:
     - name: Build fs/shell for aarch64-raspi4
       run: make PLATFORM=aarch64-raspi4 A=apps/fs/shell FEATURES=driver-bcm2835-sdhci
 
-    - name: Build hello for aarch64-bsta1000b
+    - name: Build helloworld for aarch64-bsta1000b
       run: make PLATFORM=aarch64-bsta1000b A=apps/helloworld
 
   build-apps-for-std:

crates/arm_gic/src/lib.rs

@@ -45,3 +45,47 @@ pub enum TriggerMode {
     /// level is active, and deasserted whenever the level is not active.
     Level = 1,
 }
+
+/// Different types of interrupt that the GIC handles.
+pub enum InterruptType {
+    /// Software-generated interrupt.
+    ///
+    /// SGIs are typically used for inter-processor communication and are
+    /// generated by a write to an SGI register in the GIC.
+    SGI,
+    /// Private Peripheral Interrupt.
+    ///
+    /// Peripheral interrupts that are private to one core.
+    PPI,
+    /// Shared Peripheral Interrupt.
+    ///
+    /// Peripheral interrupts that can delivered to any connected core.
+    SPI,
+}
+
+/// Translate an interrupt of a given type to a GIC INTID.
+pub const fn translate_irq(id: usize, int_type: InterruptType) -> Option<usize> {
+    match int_type {
+        InterruptType::SGI => {
+            if id < SGI_RANGE.end {
+                Some(id)
+            } else {
+                None
+            }
+        }
+        InterruptType::PPI => {
+            if id < PPI_RANGE.end - PPI_RANGE.start {
+                Some(id + PPI_RANGE.start)
+            } else {
+                None
+            }
+        }
+        InterruptType::SPI => {
+            if id < SPI_RANGE.end - SPI_RANGE.start {
+                Some(id + SPI_RANGE.start)
+            } else {
+                None
+            }
+        }
+    }
+}

modules/axhal/src/lib.rs

@@ -28,6 +28,7 @@
 #![feature(asm_const)]
 #![feature(naked_functions)]
 #![feature(const_maybe_uninit_zeroed)]
+#![feature(const_option)]
 #![feature(doc_auto_cfg)]
 
 #[allow(unused_imports)]

modules/axhal/src/platform/aarch64_bsta1000b/dw_apb_uart.rs

@@ -35,10 +35,7 @@ pub fn init_early() {
 #[cfg(feature = "irq")]
 pub fn init_irq() {
     UART.lock().set_ier(true);
-
-    use crate::platform::aarch64_common::gic::{gic_irq_tran, IntIdType};
-    // IRQ Type: SPI
-    crate::irq::register_handler(gic_irq_tran(axconfig::UART_IRQ_NUM, IntIdType::SPI), handle);
+    crate::irq::register_handler(crate::platform::irq::UART_IRQ_NUM, handle);
 }
 
 /// UART IRQ Handler

modules/axhal/src/platform/aarch64_common/gic.rs

@@ -1,14 +1,17 @@
 use crate::{irq::IrqHandler, mem::phys_to_virt};
 use arm_gic::gic_v2::{GicCpuInterface, GicDistributor};
+use arm_gic::{translate_irq, InterruptType};
 use memory_addr::PhysAddr;
 use spinlock::SpinNoIrq;
 
 /// The maximum number of IRQs.
 pub const MAX_IRQ_COUNT: usize = 1024;
 
 /// The timer IRQ number.
-/// EL1 physical timer, type=PPI, id=14
-pub const TIMER_IRQ_NUM: usize = 16 + 14;
+pub const TIMER_IRQ_NUM: usize = translate_irq(14, InterruptType::PPI).unwrap();
+
+/// The UART IRQ number.
+pub const UART_IRQ_NUM: usize = translate_irq(axconfig::UART_IRQ, InterruptType::SPI).unwrap();
 
 const GICD_BASE: PhysAddr = PhysAddr::from(axconfig::GICD_PADDR);
 const GICC_BASE: PhysAddr = PhysAddr::from(axconfig::GICC_PADDR);
@@ -19,33 +22,9 @@ static GICD: SpinNoIrq<GicDistributor> =
 // per-CPU, no lock
 static GICC: GicCpuInterface = GicCpuInterface::new(phys_to_virt(GICC_BASE).as_mut_ptr());
 
-#[allow(dead_code)]
-pub enum IntIdType {
-    LPI = 0,
-    PPI = 16,
-    SPI = 32,
-    EPPI = 1056,
-    ESPI = 4096,
-}
-
-/// Translate a GIC irq domain hardware interrupt ID into the real ID
-#[allow(dead_code)]
-pub fn gic_irq_tran(hwirq: usize, int_id_type: IntIdType) -> usize {
-    match int_id_type {
-        IntIdType::PPI => hwirq + IntIdType::PPI as usize,
-        IntIdType::SPI => hwirq + IntIdType::SPI as usize,
-        IntIdType::EPPI => hwirq + IntIdType::EPPI as usize,
-        IntIdType::ESPI => hwirq + IntIdType::ESPI as usize,
-        _ => {
-            warn!("Unknown interrupt ID type: {}", int_id_type as usize);
-            hwirq
-        }
-    }
-}
-
 /// Enables or disables the given IRQ.
 pub fn set_enable(irq_num: usize, enabled: bool) {
-    trace!("GICD set enable {} {}", irq_num, enabled);
+    trace!("GICD set enable: {} {}", irq_num, enabled);
     GICD.lock().set_enable(irq_num as _, enabled);
 }
 

modules/axhal/src/platform/aarch64_common/pl011.rs

@@ -36,7 +36,7 @@ pub fn init_early() {
 /// Set UART IRQ Enable
 pub fn init() {
     #[cfg(feature = "irq")]
-    crate::platform::irq::set_enable(axconfig::UART_IRQ_NUM, true);
+    crate::irq::set_enable(crate::platform::irq::UART_IRQ_NUM, true);
 }
 
 /// UART IRQ Handler

platforms/aarch64-bsta1000b.toml

@@ -38,7 +38,7 @@ virtio-mmio-regions = []
 # UART Address
 uart-paddr = "0x20008000"
 # UART irq from device tree
-uart-irq-num = "213"
+uart-irq = "0xd5"
 # GICD Address
 gicd-paddr = "0x32001000"
 # GICC Address

platforms/aarch64-qemu-virt.toml

@@ -71,7 +71,7 @@ pci-ranges = [
 ]
 # UART Address
 uart-paddr = "0x0900_0000"
-uart-irq-num = "33"
+uart-irq = "1"
 
 # GICC Address
 gicc-paddr = "0x0801_0000"

platforms/aarch64-raspi4.toml

@@ -24,7 +24,7 @@ mmio-regions = [
 virtio-mmio-regions = []
 # UART Address
 uart-paddr = "0xFE20_1000"
-uart-irq-num = "153"
+uart-irq = "0x79"
 
 # GIC Address
 gicc-paddr = "0xFF84_2000"