Added documentation and corrected CHANGELOG.md

CHANGELOG.md

@@ -5,7 +5,7 @@
 - [\#689](https://github.com/arkworks-rs/algebra/pull/689) (`ark-serialize`) Add `CanonicalSerialize` and `CanonicalDeserialize` impls for `VecDeque` and `LinkedList`.
 - [\#693](https://github.com/arkworks-rs/algebra/pull/693) (`ark-serialize`) Add `serialize_to_vec!` convenience macro.
 - [\#713](https://github.com/arkworks-rs/algebra/pull/713) (`ark-ff`) Add support for bitwise operations AND, OR, and XOR between `BigInteger`.
-- [\#736](https://github.com/arkworks-rs/algebra/pull/736) (`ark-ff`) Deprecate the use of `muln()` and `divn()`. Instead, it is implemented the traits `core::ops::Shl` and `core::ops::Shr` respectively.
+- [\#736](https://github.com/arkworks-rs/algebra/pull/736) (`ark-ff`) Deprecate the use of `divn()`. Instead, it is implemented the trait `core::ops::Shr`.
 
 ### Breaking changes
 

ff/src/biginteger/mod.rs

@@ -732,6 +732,11 @@ impl<B: Borrow<Self>, const N: usize> BitOr<B> for BigInt<N> {
 impl<const N: usize> Shr<u32> for BigInt<N> {
     type Output = Self;
 
+    /// Computes bitwise shift right operation.
+    /// 
+    /// Differently from the built-in numeric types (u8, u32, u64, etc.) this
+    /// operation does *not* return an underflow error if the number of bits
+    /// shifted is larger than N * 64.
     fn shr(self, mut rhs: u32) -> Self::Output {
         let mut data = self.0.clone();