Electronic Projects Versioning Repo

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adder
  Some Verilog Code for Adders / Multipliers

complimenter
  One input, one output serial 2's complementer.

tls
  Traffic Light System

astable_calculator
	Calculator for the RC requirements to create an Astable 555 Timer.
	Implemented in C, CPP, Javascript, Python and simulation using Circuit Wizard.

electrical 
	Several Spice codes used for EE 131 tutorials.

fsm
	Project in EE 177 (Simpson's Sensor)
	Finite State Machine 
	Verilog implementation

jverilog
	Verilog compiler IDE using iVerilog on the backend.