Fix MISRA C issues in BL1/BL2/BL31

Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code. Mainly issues like not using boolean expressions in conditionals, conflicting variable names, ignoring return values without (void), adding explicit casts, etc. Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a Signed-off-by: John Powell <[email protected]>
bao-project · Apr 3, 2020 · 3443a70 · 3443a70
1 parent 0f99bf3
commit 3443a70
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Showing 10 changed files with 172 additions and 162 deletions.
diff --git a/bl1/aarch32/bl1_context_mgmt.c b/bl1/aarch32/bl1_context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -53,10 +53,10 @@ void *cm_get_context(uint32_t security_state)
 	return &bl1_cpu_context[security_state];
 }
 
-void cm_set_next_context(void *cpu_context)
+void cm_set_next_context(void *context)
 {
-	assert(cpu_context);
-	bl1_next_cpu_context_ptr = cpu_context;
+	assert(context != NULL);
+	bl1_next_cpu_context_ptr = context;
 }
 
 void *cm_get_next_context(void)
@@ -103,21 +103,21 @@ static void flush_smc_and_cpu_ctx(void)
 void bl1_prepare_next_image(unsigned int image_id)
 {
 	unsigned int security_state, mode = MODE32_svc;
-	image_desc_t *image_desc;
+	image_desc_t *desc;
 	entry_point_info_t *next_bl_ep;
 
 	/* Get the image descriptor. */
-	image_desc = bl1_plat_get_image_desc(image_id);
-	assert(image_desc);
+	desc = bl1_plat_get_image_desc(image_id);
+	assert(desc != NULL);
 
 	/* Get the entry point info. */
-	next_bl_ep = &image_desc->ep_info;
+	next_bl_ep = &desc->ep_info;
 
 	/* Get the image security state. */
 	security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
 
 	/* Prepare the SPSR for the next BL image. */
-	if ((security_state != SECURE) && (GET_VIRT_EXT(read_id_pfr1()))) {
+	if ((security_state != SECURE) && (GET_VIRT_EXT(read_id_pfr1()) != 0U)) {
 		mode = MODE32_hyp;
 	}
 
@@ -166,7 +166,7 @@ void bl1_prepare_next_image(unsigned int image_id)
 	flush_smc_and_cpu_ctx();
 
 	/* Indicate that image is in execution state. */
-	image_desc->state = IMAGE_STATE_EXECUTED;
+	desc->state = IMAGE_STATE_EXECUTED;
 
 	print_entry_point_info(next_bl_ep);
 }
diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c
@@ -43,7 +43,7 @@ void cm_set_context(void *context, uint32_t security_state)
 void bl1_prepare_next_image(unsigned int image_id)
 {
 	unsigned int security_state, mode = MODE_EL1;
-	image_desc_t *image_desc;
+	image_desc_t *desc;
 	entry_point_info_t *next_bl_ep;
 
 #if CTX_INCLUDE_AARCH32_REGS
@@ -59,11 +59,11 @@ void bl1_prepare_next_image(unsigned int image_id)
 #endif
 
 	/* Get the image descriptor. */
-	image_desc = bl1_plat_get_image_desc(image_id);
-	assert(image_desc);
+	desc = bl1_plat_get_image_desc(image_id);
+	assert(desc != NULL);
 
 	/* Get the entry point info. */
-	next_bl_ep = &image_desc->ep_info;
+	next_bl_ep = &desc->ep_info;
 
 	/* Get the image security state. */
 	security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
@@ -77,7 +77,7 @@ void bl1_prepare_next_image(unsigned int image_id)
 		mode = MODE_EL2;
 	}
 
-	next_bl_ep->spsr = SPSR_64(mode, MODE_SP_ELX,
+	next_bl_ep->spsr = (uint32_t)SPSR_64(mode, MODE_SP_ELX,
 		DISABLE_ALL_EXCEPTIONS);
 
 	/* Allow platform to make change */
@@ -88,7 +88,7 @@ void bl1_prepare_next_image(unsigned int image_id)
 	cm_prepare_el3_exit(security_state);
 
 	/* Indicate that image is in execution state. */
-	image_desc->state = IMAGE_STATE_EXECUTED;
+	desc->state = IMAGE_STATE_EXECUTED;
 
 	print_entry_point_info(next_bl_ep);
 }