Skip to content

Commit

Permalink
style: format all files using clang-format
Browse files Browse the repository at this point in the history 
Signed-off-by: Jose Martins <[email protected]>
  • Loading branch information
@josecm
josecm committed Oct 27, 2023
1 parent 88b1cb1 commit a2c0176
Show file tree
Hide file tree
Showing 182 changed files with 6,114 additions and 6,146 deletions.
6 changes: 3 additions & 3 deletions src/arch/armv8/aarch32/aborts.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,9 @@
#include <arch/sysregs.h>
#include <cpu.h>

void internal_abort_handler(unsigned long gprs[]) {

for(ssize_t i = 14; i >= 0; i--) {
void internal_abort_handler(unsigned long gprs[])
{
for (ssize_t i = 14; i >= 0; i--) {
console_printk("x%d:\t\t0x%0lx\n", i, gprs[14 - i]);
}
console_printk("ESR:\t0x%0lx\n", sysreg_esr_el2_read());
Expand Down
11 changes: 4 additions & 7 deletions src/arch/armv8/aarch32/inc/arch/spinlock.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ typedef struct {
uint32_t next;
} spinlock_t;

#define SPINLOCK_INITVAL ((spinlock_t){0,0})
#define SPINLOCK_INITVAL ((spinlock_t){ 0, 0 })

static inline void spinlock_init(spinlock_t* lock)
{
Expand Down Expand Up @@ -48,9 +48,8 @@ static inline void spin_lock(spinlock_t* lock)
"beq 3f\n\t"
"wfe \n\t"
"b 2b\n\t"
"3:\n\t"
: "=&r"(ticket), "=&r"(next), "=&r"(temp)
: "Q"(lock->ticket), "Q"(lock->next) : "memory");
"3:\n\t" : "=&r"(ticket), "=&r"(next), "=&r"(temp) : "Q"(lock->ticket), "Q"(lock->next)
: "memory");
}

static inline void spin_unlock(spinlock_t* lock)
Expand All @@ -63,9 +62,7 @@ static inline void spin_unlock(spinlock_t* lock)
"add %r0, %r0, #1\n\t"
"stl %r0, %1\n\t"
"dsb ish\n\t"
"sev\n\t"
: "=&r"(temp)
: "Q"(lock->next) : "memory");
"sev\n\t" : "=&r"(temp) : "Q"(lock->next) : "memory");
}

#endif /* __ARCH_SPINLOCK__ */
119 changes: 66 additions & 53 deletions src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,50 +10,56 @@

#ifndef __ASSEMBLER__

#define SYSREG_GEN_ACCESSORS(name, op1, crn, crm, op2) \
static inline unsigned long sysreg_##name##_read() {\
unsigned long _temp;\
asm volatile("mrc p15, "#op1", %0, "#crn", "#crm", %1\n\r": "=r"(_temp): "i"(op2));\
return _temp;\
} \
static inline void sysreg_##name##_write(unsigned long val) {\
asm volatile("mcr p15, "#op1", %0, "#crn", "#crm", "#op2"\n\r": :"r"((val)));\
#define SYSREG_GEN_ACCESSORS(name, op1, crn, crm, op2) \
static inline unsigned long sysreg_##name##_read() \
{ \
unsigned long _temp; \
asm volatile("mrc p15, " #op1 ", %0, " #crn ", " #crm ", %1\n\r" : "=r"(_temp) : "i"(op2)); \
return _temp; \
} \
static inline void sysreg_##name##_write(unsigned long val) \
{ \
asm volatile("mcr p15, " #op1 ", %0, " #crn ", " #crm ", " #op2 "\n\r" : : "r"(val)); \
}

#define SYSREG_GEN_ACCESSORS_BANKED(name, reg) \
static inline unsigned long sysreg_##name##_read() {\
unsigned long _temp;\
asm volatile("mrs %0, " XSTR(reg) "\n\r": "=r"(_temp));\
return _temp;\
} \
static inline void sysreg_##name##_write(unsigned long val) {\
asm volatile("msr " XSTR(reg) ", %0\n\r": :"r"((val)));\
#define SYSREG_GEN_ACCESSORS_BANKED(name, reg) \
static inline unsigned long sysreg_##name##_read() \
{ \
unsigned long _temp; \
asm volatile("mrs %0, " XSTR(reg) "\n\r" : "=r"(_temp)); \
return _temp; \
} \
static inline void sysreg_##name##_write(unsigned long val) \
{ \
asm volatile("msr " XSTR(reg) ", %0\n\r" : : "r"(val)); \
}

#define SYSREG_GEN_ACCESSORS_64(reg, op1, crm) \
static inline unsigned long long sysreg_##reg##_read() {\
unsigned long long _temp, _tempH;\
asm volatile("mrrc p15, "#op1", %0, %1, "#crm"\n\r": "=r"(_temp), "=r"(_tempH));\
return ((_tempH << 32) | _temp);\
} \
static inline void sysreg_##reg##_write(unsigned long long val) {\
unsigned long long _tempH = (val>>32);\
asm volatile("mcrr p15, "#op1", %0, %1, "#crm"\n\r": :"r"(val), "r"(_tempH));\
#define SYSREG_GEN_ACCESSORS_64(reg, op1, crm) \
static inline unsigned long long sysreg_##reg##_read() \
{ \
unsigned long long _temp, _tempH; \
asm volatile("mrrc p15, " #op1 ", %0, %1, " #crm "\n\r" : "=r"(_temp), "=r"(_tempH)); \
return ((_tempH << 32) | _temp); \
} \
static inline void sysreg_##reg##_write(unsigned long long val) \
{ \
unsigned long long _tempH = (val >> 32); \
asm volatile("mcrr p15, " #op1 ", %0, %1, " #crm "\n\r" : : "r"(val), "r"(_tempH)); \
}

#define SYSREG_GEN_ACCESSORS_MERGE(reg, reg1, reg2) \
static inline unsigned long long sysreg_##reg##_read() {\
return ((unsigned long long)sysreg_##reg2##_read() << 32) |\
sysreg_##reg1##_read();\
}\
static inline void sysreg_##reg##_write(unsigned long long val) {\
sysreg_##reg1##_write(val);\
sysreg_##reg2##_write(val >> 32);\
#define SYSREG_GEN_ACCESSORS_MERGE(reg, reg1, reg2) \
static inline unsigned long long sysreg_##reg##_read() \
{ \
return ((unsigned long long)sysreg_##reg2##_read() << 32) | sysreg_##reg1##_read(); \
} \
static inline void sysreg_##reg##_write(unsigned long long val) \
{ \
sysreg_##reg1##_write(val); \
sysreg_##reg2##_write(val >> 32); \
}


/**
* We give aarch32 registers the same name as aarch64's to which they are
* We give aarch32 registers the same name as aarch64's to which they are
* architecturally mapped to, so that we can use the same name in common code.
*/
SYSREG_GEN_ACCESSORS(esr_el2, 4, c5, c2, 0); // hsr
Expand All @@ -66,13 +72,13 @@ SYSREG_GEN_ACCESSORS(ctr_el0, 0, c0, c0, 1);
SYSREG_GEN_ACCESSORS(mpidr_el1, 0, c0, c0, 5);
SYSREG_GEN_ACCESSORS(vmpidr_el2, 4, c0, c0, 5);
SYSREG_GEN_ACCESSORS_64(cntvoff_el2, 4, c14);
SYSREG_GEN_ACCESSORS(sctlr_el1, 0, c1, c0, 0);
SYSREG_GEN_ACCESSORS(sctlr_el1, 0, c1, c0, 0);
SYSREG_GEN_ACCESSORS(cntkctl_el1, 0, c14, c1, 0);
SYSREG_GEN_ACCESSORS(pmcr_el0, 0, c9, c12, 0);
SYSREG_GEN_ACCESSORS_64(par_el1, 0, c7);
SYSREG_GEN_ACCESSORS(tcr_el2, 4, c2, c0, 2); // htcr
SYSREG_GEN_ACCESSORS_64(ttbr0_el2, 4, c2); // httbr
SYSREG_GEN_ACCESSORS(cptr_el2, 4, c1, c1, 2); // hcptr
SYSREG_GEN_ACCESSORS(tcr_el2, 4, c2, c0, 2); // htcr
SYSREG_GEN_ACCESSORS_64(ttbr0_el2, 4, c2); // httbr
SYSREG_GEN_ACCESSORS(cptr_el2, 4, c1, c1, 2); // hcptr
SYSREG_GEN_ACCESSORS(vtcr_el2, 4, c2, c1, 2);
SYSREG_GEN_ACCESSORS_64(vttbr_el2, 6, c2);
SYSREG_GEN_ACCESSORS(tpidr_el2, 4, c13, c0, 2); // htpidr
Expand Down Expand Up @@ -109,10 +115,10 @@ SYSREG_GEN_ACCESSORS_64(icc_sgi1r_el1, 0, c12);

SYSREG_GEN_ACCESSORS(vsctlr_el2, 4, c2, c0, 0);

#define SYSREG_GEN_GIC_LR(n, crn1, crn2, op2) \
SYSREG_GEN_ACCESSORS(ich_lr##n, 4, c12, crn1, op2); \
#define SYSREG_GEN_GIC_LR(n, crn1, crn2, op2) \
SYSREG_GEN_ACCESSORS(ich_lr##n, 4, c12, crn1, op2); \
SYSREG_GEN_ACCESSORS(ich_lrc##n, 4, c12, crn2, op2); \
SYSREG_GEN_ACCESSORS_MERGE(ich_lr##n##_el2, ich_lr##n, ich_lrc##n); \
SYSREG_GEN_ACCESSORS_MERGE(ich_lr##n##_el2, ich_lr##n, ich_lrc##n);

SYSREG_GEN_GIC_LR(0, c12, c14, 0);
SYSREG_GEN_GIC_LR(1, c12, c14, 1);
Expand All @@ -132,32 +138,39 @@ SYSREG_GEN_GIC_LR(14, c13, c15, 6);
SYSREG_GEN_GIC_LR(15, c13, c15, 7);

SYSREG_GEN_ACCESSORS(dccivac, 0, c7, c14, 1);
static inline void arm_dc_civac(vaddr_t cache_addr) {
static inline void arm_dc_civac(vaddr_t cache_addr)
{
sysreg_dccivac_write(cache_addr);
}

static inline void arm_at_s1e2w(vaddr_t vaddr) {
asm volatile("mcr p15, 4, %0, c7, c8, 1" ::"r"(vaddr)); // ats1hw
static inline void arm_at_s1e2w(vaddr_t vaddr)
{
asm volatile("mcr p15, 4, %0, c7, c8, 1" ::"r"(vaddr)); // ats1hw
}

static inline void arm_at_s12e1w(vaddr_t vaddr) {
asm volatile("mcr p15, 0, %0, c7, c8, 5" ::"r"(vaddr)); // ats12nsopw
static inline void arm_at_s12e1w(vaddr_t vaddr)
{
asm volatile("mcr p15, 0, %0, c7, c8, 5" ::"r"(vaddr)); // ats12nsopw
}

static inline void arm_tlbi_alle2is() {
static inline void arm_tlbi_alle2is()
{
asm volatile("mcr p15, 4, r0, c8, c7, 0");
}

static inline void arm_tlbi_vmalls12e1is() {
static inline void arm_tlbi_vmalls12e1is()
{
asm volatile("mcr p15, 0, r0, c8, c7, 0");
}

static inline void arm_tlbi_vae2is(vaddr_t vaddr) {
asm volatile("mcr p15, 4, %0, c8, c7, 1" :: "r"(vaddr));
static inline void arm_tlbi_vae2is(vaddr_t vaddr)
{
asm volatile("mcr p15, 4, %0, c8, c7, 1" ::"r"(vaddr));
}

static inline void arm_tlbi_ipas2e1is(vaddr_t vaddr) {
asm volatile("mcr p15, 4, %0, c8, c0, 1" :: "r"(vaddr >> 12));
static inline void arm_tlbi_ipas2e1is(vaddr_t vaddr)
{
asm volatile("mcr p15, 4, %0, c8, c0, 1" ::"r"(vaddr >> 12));
}

#endif /* |__ASSEMBLER__ */
Expand Down
11 changes: 8 additions & 3 deletions src/arch/armv8/aarch32/vm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,13 +8,17 @@

unsigned long vcpu_readreg(struct vcpu* vcpu, unsigned long reg)
{
if (reg > 14) return 0;
if (reg > 14) {
return 0;
}
return vcpu->regs.x[reg];
}

void vcpu_writereg(struct vcpu* vcpu, unsigned long reg, unsigned long val)
{
if (reg > 14) return;
if (reg > 14) {
return;
}
vcpu->regs.x[reg] = val;
}

Expand All @@ -28,6 +32,7 @@ void vcpu_writepc(struct vcpu* vcpu, unsigned long pc)
vcpu->regs.elr_hyp = pc;
}

void vcpu_subarch_reset(struct vcpu* vcpu) {
void vcpu_subarch_reset(struct vcpu* vcpu)
{
vcpu->regs.spsr_hyp = SPSR_SVC | SPSR_F | SPSR_I | SPSR_A;
}
6 changes: 3 additions & 3 deletions src/arch/armv8/aarch64/aborts.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,9 @@
#include <arch/sysregs.h>
#include <cpu.h>

void internal_abort_handler(unsigned long gprs[]) {

for(size_t i = 0; i < 31; i++) {
void internal_abort_handler(unsigned long gprs[])
{
for (size_t i = 0; i < 31; i++) {
console_printk("x%d:\t\t0x%0lx\n", i, gprs[i]);
}
console_printk("SP:\t\t0x%0lx\n", gprs[31]);
Expand Down
12 changes: 4 additions & 8 deletions src/arch/armv8/aarch64/inc/arch/spinlock.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ typedef struct {
uint32_t next;
} spinlock_t;

#define SPINLOCK_INITVAL ((spinlock_t){0,0})
#define SPINLOCK_INITVAL ((spinlock_t){ 0, 0 })

static inline void spinlock_init(spinlock_t* lock)
{
Expand Down Expand Up @@ -47,9 +47,8 @@ static inline void spin_lock(spinlock_t* lock)
"b.eq 3f\n\t"
"wfe\n\t"
"b 2b\n\t"
"3:\n\t"
: "=&r"(ticket), "=&r"(next), "=&r"(temp)
: "Q"(lock->ticket), "Q"(lock->next) : "memory");
"3:\n\t" : "=&r"(ticket), "=&r"(next), "=&r"(temp) : "Q"(lock->ticket), "Q"(lock->next)
: "memory");
}

static inline void spin_unlock(spinlock_t* lock)
Expand All @@ -62,10 +61,7 @@ static inline void spin_unlock(spinlock_t* lock)
"add %w0, %w0, 1\n\t"
"stlr %w0, %1\n\t"
"dsb ish\n\t"
"sev\n\t"
: "=&r"(temp)
: "Q"(lock->next) : "memory");
"sev\n\t" : "=&r"(temp) : "Q"(lock->next) : "memory");
}


#endif /* __ARCH_SPINLOCK__ */
Loading

0 comments on commit a2c0176

Please sign in to comment.