Format code using clang format and introduce CI checks for it

.github/workflows/code-quality.yaml

@@ -0,0 +1,19 @@
+name: Code Quality
+
+on:
+  push:
+    branches: [ main ]
+  pull_request:
+  workflow_dispatch:
+
+jobs:
+
+  coding-style:
+    runs-on: ubuntu-latest
+    container: baoproject/bao:latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          fetch-depth: 0
+          submodules: recursive
+      - run: make format-check

Makefile

@@ -307,8 +307,12 @@ all_files= $(realpath \
 	$(call list_dir_files_recursive, $(scripts_dir), *) \
 	$(call list_dir_files_recursive, $(config_dir)/example, *) \
 )
+c_src_files=$(realpath $(call list_dir_files_recursive, src, *.c))
+c_hdr_files=$(realpath $(call list_dir_files_recursive, src, *.h))
+c_files=$(c_src_files) $(c_hdr_files)
 
 $(call ci, license, "Apache-2.0", $(all_files))
+$(call ci, format, $(c_files))
 
 .PHONY: ci
-ci: license-check
+ci: license-check format-check

README.md

@@ -1,5 +1,6 @@
 # Bao - a lightweight static partitioning hypervisor
 
+![code quality workflow](https://github.com/bao-project/bao-hypervisor/actions/workflows/code-quality.yaml/badge.svg)
 ![arm build workflow](https://github.com/bao-project/bao-hypervisor/actions/workflows/build-arm.yaml/badge.svg)
 ![riscv build workflow](https://github.com/bao-project/bao-hypervisor/actions/workflows/build-riscv.yaml/badge.svg)
 

src/arch/armv8/aarch32/aborts.c

@@ -7,9 +7,9 @@
 #include <arch/sysregs.h>
 #include <cpu.h>
 
-void internal_abort_handler(unsigned long gprs[]) {
-
-    for(ssize_t i = 14; i >= 0; i--) {
+void internal_abort_handler(unsigned long gprs[])
+{
+    for (ssize_t i = 14; i >= 0; i--) {
         console_printk("x%d:\t\t0x%0lx\n", i, gprs[14 - i]);
     }
     console_printk("ESR:\t0x%0lx\n", sysreg_esr_el2_read());

src/arch/armv8/aarch32/boot.S

@@ -19,15 +19,14 @@
 .data
 .balign 4
 /**
- * barrier is used to minimal synchronization in boot - other cores wait for
- * bsp to set it.
+ * barrier is used to minimal synchronization in boot - other cores wait for bsp to set it.
  */
 _barrier: .4byte 0
 
 /**
- * 	The following code MUST be at the base of the image, as this is bao's entry
- *	point. Therefore .boot section must also be the first in the linker script.
- *  DO NOT implement any code before the _reset_handler in this section.
+ *  The following code MUST be at the base of the image, as this is bao's entry point. Therefore
+ * .boot section must also be the first in the linker script. DO NOT implement any code before the
+ * _reset_handler in this section.
  */
  .section ".boot", "ax"
 .globl _reset_handler
@@ -57,10 +56,10 @@ _reset_handler:
     adr r1, _el2_entry
 
     /**
-     * Linearize cpu id according to the number of clusters and processors
-     * per cluster. We are only considering two levels of affinity.
-     * TODO: this should be done some other way. We shouldn't depend on the platform
-     * description this early in the initialization.
+     * Linearize cpu id according to the number of clusters and processors per cluster. We are only
+     * considering two levels of affinity.
+     * TODO: this should be done some other way. We shouldn't depend on the platform description
+     * this early in the initialization.
      */
     mov r3, r0, lsr #8
     and r3, r3, #0xff
@@ -88,8 +87,8 @@ _reset_handler:
     add r0, r0, r7
 
     /*
-     * Install vector table physical address early, in case exception occurs
-     * during this initialization.
+     * Install vector table physical address early, in case exception occurs during this
+     * initialization.
      */
     get_phys_addr r3, r4, _hyp_vector_table
     mcr p15, 4, r3, c12, c0, 0 // write HVBAR
@@ -103,9 +102,9 @@ _reset_handler:
    bne 1f
 #else
 /**
- * If the cpu master is not fixed, for setting it, we assume only one cpu is
- * initially activated which later will turn on all the others. Therefore, there
- * is no concurrency when setting CPU_MASTER and no atomic operations are needed.
+ * If the cpu master is not fixed, for setting it, we assume only one cpu is initially activated
+ * which later will turn on all the others. Therefore, there is no concurrency when setting
+ * CPU_MASTER and no atomic operations are needed.
  */
  .pushsection .data
 _master_set:
@@ -124,8 +123,8 @@ _set_master_cpu:
 1:
 
     /**
-     * TODO: bring the system to a well known state. This includes disabling
-     * the MPU, all caches, BP and others, and invalidating them.
+     * TODO: bring the system to a well known state. This includes disabling the MPU, all caches,
+     * BP and others, and invalidating them.
      */
 
     /* Clear stack pointer to avoid unaligned SP exceptions during boot */
@@ -182,7 +181,7 @@ _set_master_cpu:
     /* This point should never be reached */
     b .
 
-/***** 	Helper functions for boot code. ******/
+/*****  Helper functions for boot code. ******/
 
 .global boot_clear
 .func boot_clear
@@ -199,8 +198,7 @@ boot_clear:
 .endfunc
 
 /*
- * Code adapted from "Application Note Bare-metal Boot Code for ARMv8-A
- * Processors - Version 1.0"
+ * Code adapted from "Application Note Bare-metal Boot Code for ARMv8-A Processors - Version 1.0"
  *
  * r0 - cache level to be invalidated (0 - dl1$, 1 - il1$)
  */

src/arch/armv8/aarch32/inc/arch/spinlock.h

@@ -13,7 +13,7 @@ typedef struct {
     uint32_t next;
 } spinlock_t;
 
-#define SPINLOCK_INITVAL ((spinlock_t){0,0})
+#define SPINLOCK_INITVAL ((spinlock_t){ 0, 0 })
 
 static inline void spinlock_init(spinlock_t* lock)
 {
@@ -48,9 +48,8 @@ static inline void spin_lock(spinlock_t* lock)
         "beq   3f\n\t"
         "wfe \n\t"
         "b 2b\n\t"
-        "3:\n\t"
-        : "=&r"(ticket), "=&r"(next), "=&r"(temp)
-        : "Q"(lock->ticket), "Q"(lock->next) : "memory");
+        "3:\n\t" : "=&r"(ticket), "=&r"(next), "=&r"(temp) : "Q"(lock->ticket), "Q"(lock->next)
+        : "memory");
 }
 
 static inline void spin_unlock(spinlock_t* lock)
@@ -63,9 +62,7 @@ static inline void spin_unlock(spinlock_t* lock)
         "add    %r0, %r0, #1\n\t"
         "stl    %r0, %1\n\t"
         "dsb ish\n\t"
-        "sev\n\t"
-        : "=&r"(temp)
-        : "Q"(lock->next) : "memory");
+        "sev\n\t" : "=&r"(temp) : "Q"(lock->next) : "memory");
 }
 
 #endif /* __ARCH_SPINLOCK__ */

src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h

@@ -10,51 +10,57 @@
 
 #ifndef __ASSEMBLER__
 
-#define SYSREG_GEN_ACCESSORS(name, op1, crn, crm, op2) \
-    static inline unsigned long sysreg_##name##_read() {\
-        unsigned long _temp;\
-        asm volatile("mrc p15, "#op1", %0, "#crn", "#crm", %1\n\r": "=r"(_temp): "i"(op2));\
-        return _temp;\
-    } \
-    static inline void sysreg_##name##_write(unsigned long val) {\
-        asm volatile("mcr p15, "#op1", %0, "#crn", "#crm", "#op2"\n\r": :"r"((val)));\
+#define SYSREG_GEN_ACCESSORS(name, op1, crn, crm, op2)                                              \
+    static inline unsigned long sysreg_##name##_read()                                              \
+    {                                                                                               \
+        unsigned long _temp;                                                                        \
+        asm volatile("mrc p15, " #op1 ", %0, " #crn ", " #crm ", %1\n\r" : "=r"(_temp) : "i"(op2)); \
+        return _temp;                                                                               \
+    }                                                                                               \
+    static inline void sysreg_##name##_write(unsigned long val)                                     \
+    {                                                                                               \
+        asm volatile("mcr p15, " #op1 ", %0, " #crn ", " #crm ", " #op2 "\n\r" : : "r"(val));       \
     }
 
-#define SYSREG_GEN_ACCESSORS_BANKED(name, reg) \
-    static inline unsigned long sysreg_##name##_read() {\
-        unsigned long _temp;\
-        asm volatile("mrs %0, " XSTR(reg) "\n\r": "=r"(_temp));\
-        return _temp;\
-    } \
-    static inline void sysreg_##name##_write(unsigned long val) {\
-        asm volatile("msr " XSTR(reg) ", %0\n\r": :"r"((val)));\
+#define SYSREG_GEN_ACCESSORS_BANKED(name, reg)                   \
+    static inline unsigned long sysreg_##name##_read()           \
+    {                                                            \
+        unsigned long _temp;                                     \
+        asm volatile("mrs %0, " XSTR(reg) "\n\r" : "=r"(_temp)); \
+        return _temp;                                            \
+    }                                                            \
+    static inline void sysreg_##name##_write(unsigned long val)  \
+    {                                                            \
+        asm volatile("msr " XSTR(reg) ", %0\n\r" : : "r"(val));  \
     }
 
-#define SYSREG_GEN_ACCESSORS_64(reg, op1, crm) \
-    static inline unsigned long long sysreg_##reg##_read() {\
-        unsigned long long _temp, _tempH;\
-        asm volatile("mrrc p15, "#op1", %0, %1, "#crm"\n\r": "=r"(_temp), "=r"(_tempH));\
-        return ((_tempH << 32) | _temp);\
-    } \
-    static inline void sysreg_##reg##_write(unsigned long long val) {\
-        unsigned long long _tempH = (val>>32);\
-        asm volatile("mcrr p15, "#op1", %0, %1, "#crm"\n\r": :"r"(val), "r"(_tempH));\
+#define SYSREG_GEN_ACCESSORS_64(reg, op1, crm)                                                \
+    static inline unsigned long long sysreg_##reg##_read()                                    \
+    {                                                                                         \
+        unsigned long long _temp, _tempH;                                                     \
+        asm volatile("mrrc p15, " #op1 ", %0, %1, " #crm "\n\r" : "=r"(_temp), "=r"(_tempH)); \
+        return ((_tempH << 32) | _temp);                                                      \
+    }                                                                                         \
+    static inline void sysreg_##reg##_write(unsigned long long val)                           \
+    {                                                                                         \
+        unsigned long long _tempH = (val >> 32);                                              \
+        asm volatile("mcrr p15, " #op1 ", %0, %1, " #crm "\n\r" : : "r"(val), "r"(_tempH));   \
     }
 
-#define SYSREG_GEN_ACCESSORS_MERGE(reg, reg1, reg2) \
-    static inline unsigned long long sysreg_##reg##_read() {\
-        return ((unsigned long long)sysreg_##reg2##_read() << 32) |\
-            sysreg_##reg1##_read();\
-    }\
-    static inline void sysreg_##reg##_write(unsigned long long val) {\
-        sysreg_##reg1##_write(val);\
-        sysreg_##reg2##_write(val >> 32);\
+#define SYSREG_GEN_ACCESSORS_MERGE(reg, reg1, reg2)                                         \
+    static inline unsigned long long sysreg_##reg##_read()                                  \
+    {                                                                                       \
+        return ((unsigned long long)sysreg_##reg2##_read() << 32) | sysreg_##reg1##_read(); \
+    }                                                                                       \
+    static inline void sysreg_##reg##_write(unsigned long long val)                         \
+    {                                                                                       \
+        sysreg_##reg1##_write(val);                                                         \
+        sysreg_##reg2##_write(val >> 32);                                                   \
     }
 
-
 /**
- * We give aarch32 registers the same name as aarch64's to which they are 
- * architecturally mapped to, so that we can use the same name in common code.
+ * We give aarch32 registers the same name as aarch64's to which they are architecturally mapped
+ * to, so that we can use the same name in common code.
  */
 SYSREG_GEN_ACCESSORS(esr_el2, 4, c5, c2, 0); // hsr
 SYSREG_GEN_ACCESSORS_BANKED(elr_el2, elr_hyp);
@@ -66,13 +72,13 @@ SYSREG_GEN_ACCESSORS(ctr_el0, 0, c0, c0, 1);
 SYSREG_GEN_ACCESSORS(mpidr_el1, 0, c0, c0, 5);
 SYSREG_GEN_ACCESSORS(vmpidr_el2, 4, c0, c0, 5);
 SYSREG_GEN_ACCESSORS_64(cntvoff_el2, 4, c14);
-SYSREG_GEN_ACCESSORS(sctlr_el1, 0, c1, c0, 0); 
+SYSREG_GEN_ACCESSORS(sctlr_el1, 0, c1, c0, 0);
 SYSREG_GEN_ACCESSORS(cntkctl_el1, 0, c14, c1, 0);
 SYSREG_GEN_ACCESSORS(pmcr_el0, 0, c9, c12, 0);
 SYSREG_GEN_ACCESSORS_64(par_el1, 0, c7);
-SYSREG_GEN_ACCESSORS(tcr_el2, 4, c2, c0, 2); // htcr
-SYSREG_GEN_ACCESSORS_64(ttbr0_el2, 4, c2); // httbr
-SYSREG_GEN_ACCESSORS(cptr_el2, 4, c1, c1, 2); // hcptr
+SYSREG_GEN_ACCESSORS(tcr_el2, 4, c2, c0, 2);    // htcr
+SYSREG_GEN_ACCESSORS_64(ttbr0_el2, 4, c2);      // httbr
+SYSREG_GEN_ACCESSORS(cptr_el2, 4, c1, c1, 2);   // hcptr
 SYSREG_GEN_ACCESSORS(vtcr_el2, 4, c2, c1, 2);
 SYSREG_GEN_ACCESSORS_64(vttbr_el2, 6, c2);
 SYSREG_GEN_ACCESSORS(tpidr_el2, 4, c13, c0, 2); // htpidr
@@ -109,10 +115,10 @@ SYSREG_GEN_ACCESSORS_64(icc_sgi1r_el1, 0, c12);
 
 SYSREG_GEN_ACCESSORS(vsctlr_el2, 4, c2, c0, 0);
 
-#define SYSREG_GEN_GIC_LR(n, crn1, crn2, op2) \
-    SYSREG_GEN_ACCESSORS(ich_lr##n, 4, c12, crn1, op2); \
+#define SYSREG_GEN_GIC_LR(n, crn1, crn2, op2)            \
+    SYSREG_GEN_ACCESSORS(ich_lr##n, 4, c12, crn1, op2);  \
     SYSREG_GEN_ACCESSORS(ich_lrc##n, 4, c12, crn2, op2); \
-    SYSREG_GEN_ACCESSORS_MERGE(ich_lr##n##_el2, ich_lr##n, ich_lrc##n); \
+    SYSREG_GEN_ACCESSORS_MERGE(ich_lr##n##_el2, ich_lr##n, ich_lrc##n);
 
 SYSREG_GEN_GIC_LR(0, c12, c14, 0);
 SYSREG_GEN_GIC_LR(1, c12, c14, 1);
@@ -132,32 +138,39 @@ SYSREG_GEN_GIC_LR(14, c13, c15, 6);
 SYSREG_GEN_GIC_LR(15, c13, c15, 7);
 
 SYSREG_GEN_ACCESSORS(dccivac, 0, c7, c14, 1);
-static inline void arm_dc_civac(vaddr_t cache_addr) {
+static inline void arm_dc_civac(vaddr_t cache_addr)
+{
     sysreg_dccivac_write(cache_addr);
 }
 
-static inline void arm_at_s1e2w(vaddr_t vaddr) {
-     asm volatile("mcr p15, 4, %0, c7, c8, 1" ::"r"(vaddr)); // ats1hw
+static inline void arm_at_s1e2w(vaddr_t vaddr)
+{
+    asm volatile("mcr p15, 4, %0, c7, c8, 1" ::"r"(vaddr)); // ats1hw
 }
 
-static inline void arm_at_s12e1w(vaddr_t vaddr) {
-     asm volatile("mcr p15, 0, %0, c7, c8, 5" ::"r"(vaddr)); // ats12nsopw
+static inline void arm_at_s12e1w(vaddr_t vaddr)
+{
+    asm volatile("mcr p15, 0, %0, c7, c8, 5" ::"r"(vaddr)); // ats12nsopw
 }
 
-static inline void arm_tlbi_alle2is() {
+static inline void arm_tlbi_alle2is()
+{
     asm volatile("mcr p15, 4, r0, c8, c7, 0");
 }
 
-static inline void arm_tlbi_vmalls12e1is() {
+static inline void arm_tlbi_vmalls12e1is()
+{
     asm volatile("mcr p15, 0, r0, c8, c7, 0");
 }
 
-static inline void arm_tlbi_vae2is(vaddr_t vaddr) {
-    asm volatile("mcr p15, 4, %0, c8, c7, 1" :: "r"(vaddr));
+static inline void arm_tlbi_vae2is(vaddr_t vaddr)
+{
+    asm volatile("mcr p15, 4, %0, c8, c7, 1" ::"r"(vaddr));
 }
 
-static inline void arm_tlbi_ipas2e1is(vaddr_t vaddr) {
-    asm volatile("mcr p15, 4, %0, c8, c0, 1" :: "r"(vaddr >> 12));
+static inline void arm_tlbi_ipas2e1is(vaddr_t vaddr)
+{
+    asm volatile("mcr p15, 4, %0, c8, c0, 1" ::"r"(vaddr >> 12));
 }
 
 #endif /* |__ASSEMBLER__ */

src/arch/armv8/aarch32/vm.c

@@ -8,13 +8,17 @@
 
 unsigned long vcpu_readreg(struct vcpu* vcpu, unsigned long reg)
 {
-    if (reg > 14) return 0;
+    if (reg > 14) {
+        return 0;
+    }
     return vcpu->regs.x[reg];
 }
 
 void vcpu_writereg(struct vcpu* vcpu, unsigned long reg, unsigned long val)
 {
-    if (reg > 14) return;
+    if (reg > 14) {
+        return;
+    }
     vcpu->regs.x[reg] = val;
 }
 
@@ -28,6 +32,7 @@ void vcpu_writepc(struct vcpu* vcpu, unsigned long pc)
     vcpu->regs.elr_hyp = pc;
 }
 
-void vcpu_subarch_reset(struct vcpu* vcpu) {
+void vcpu_subarch_reset(struct vcpu* vcpu)
+{
     vcpu->regs.spsr_hyp = SPSR_SVC | SPSR_F | SPSR_I | SPSR_A;
 }