Again trying another detection method for other nodes' CC resets.

bittide · Oct 28, 2024 · 10b23cf · 10b23cf
1 parent bd86c13
commit 10b23cf
Showing 1 changed file with 44 additions and 28 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs
@@ -68,7 +68,7 @@ import Clash.Annotations.TH (makeTopEntity)
 import Clash.Class.Counter
 import Clash.Cores.Xilinx.GTH
 import Clash.Cores.Xilinx.Ila (Depth (..), IlaConfig (..), ila, ilaConfig)
--- import Clash.Cores.Xilinx.Xpm.Cdc (xpmCdcSingle)
+import Clash.Cores.Xilinx.Xpm.Cdc (xpmCdcSingle)
 -- import Clash.Cores.Xilinx.Xpm.Cdc.Handshake.Extra (xpmCdcMaybeLossy)
 import Clash.Functor.Extra
 import Clash.Sized.Extra (unsignedToSigned)
@@ -192,6 +192,9 @@ clockControlConfig ::
 clockControlConfig =
   $(lift (instancesClockConfig (Proxy @Basic125)))
 
+counterStartUgn :: BitVector 64
+counterStartUgn = 0xaabb_ccdd_eeff_1234
+
 -- type FifoSize = 5 -- = 2^5 = 32
 
 {- | Instantiates a hardware implementation of Callisto and exports its results. Can
@@ -250,6 +253,8 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
  where
   syncRst = rst `orReset` unsafeFromActiveHigh spiErr
 
+  allStable1 = sticky sysClk syncRst allStable0
+
   -- Clock board programming
   spiDone = E.dflipflop sysClk $ (== Finished) <$> spiState
   spiErr = E.dflipflop sysClk $ isErr <$> spiState
@@ -262,9 +267,9 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
       $ si539xSpi commonSpiConfig (SNat @(Microseconds 10)) (pure Nothing) miso
 
   txReady0 :: Vec LinkCount (Signal Basic125 Bool)
-  txReady0 = fmap go transceivers.linkReadys
+  txReady0 = zipWith go transceivers.linkReadys (unbundle $ bv2v . mask <$> cfg)
    where
-    go lR = lR .&&. notInCCReset -- if lR then notInCCReset else False
+    go lR (fmap bitToBool -> mBit) = lR .&&. mBit
   txReady1 :: Vec LinkCount (Signal GthTx Bool)
   txReady1 = zipWith (unsafeSynchronizer sysClk) transceivers.txClocks txReady0
 
@@ -288,7 +293,7 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
         -- , txDatas = txCounters
         -- , txReadys = txAllStables
         -- , rxReadys = repeat (pure True)
-        , txDatas = repeat (pure 0xDEAD_BEEF_CA55_E77E)
+        , txDatas = txCounters
         , txReadys = txReady1
         , rxReadys = repeat (pure True)
         }
@@ -301,7 +306,20 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
   transceiversFailedAfterUp =
     sticky sysClk syncRst (isFalling sysClk syncRst enableGen False allReady)
 
-  othersOutOfCCReset = isJust <<$>> transceivers.rxDatas
+  rxAllStables = zipWith (xpmCdcSingle sysClk) transceivers.rxClocks (repeat allStable1)
+  rxResets2 =
+    zipWith
+      orReset
+        transceivers.rxResets
+        (map unsafeFromActiveLow rxAllStables)
+  receivedData = zipWith3 go transceivers.rxClocks rxResets2 transceivers.rxDatas
+   where
+    go rxClk rxRst = regMaybe rxClk rxRst enableGen 0
+
+  othersShowCCResetVal = (== counterStartUgn) <<$>> receivedData
+  othersOutOfCCReset = zipWith3 go transceivers.rxClocks rxResets2 othersShowCCResetVal
+   where
+    go rxClk rxRst showsResetVal = sticky rxClk rxRst $ isFalling rxClk rxRst enableGen False showsResetVal
 
   timeSucc = countSucc @(Unsigned 16, Index (PeriodToCycles Basic125 (Milliseconds 1)))
   timer = register sysClk syncRst enableGen (0, 0) (timeSucc <$> timer)
@@ -653,29 +671,27 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
       <$> transceivers.rxClocks
       <*> transceivers.txClocks
 
-  -- txAllStables = zipWith (xpmCdcSingle sysClk) transceivers.txClocks (repeat allStable1)
-  -- allStable1 = sticky sysClk syncRst allStable0
-  -- txResets2 =
-  --   zipWith
-  --     orReset
-  --     transceivers.txResets
-  --     (map unsafeFromActiveLow txAllStables)
-
-  -- availableMask :: Vec LinkCount (Signal Basic125 Bit)
-  -- availableMask = unbundle (bv2v . mask <$> cfg)
-  -- txCounters :: Vec LinkCount (Signal GthTx (BitVector 63))
-  -- txCounters = zipWith3 txCounter transceivers.txClocks txResets2 availableMask
-  -- txCounter ::
-  --   Clock GthTx -> Reset GthTx -> Signal Basic125 Bit -> Signal GthTx (BitVector 63)
-  -- txCounter txClk txRst txMask = result
-  --  where
-  --   txMask' = unsafeSynchronizer sysClk txClk txMask
-  --   next txMaskBit = case txMaskBit of
-  --     1 -> countSucc
-  --     _ -> id
-  --   result =
-  --     register txClk txRst enableGen (0x2abb_ccdd_eeff_1234 :: BitVector 63)
-  --       $ liftA2 next txMask' result
+  txAllStables = zipWith (xpmCdcSingle sysClk) transceivers.txClocks (repeat allStable1)
+  txResets2 =
+    zipWith
+      orReset
+      transceivers.txResets
+      (map unsafeFromActiveLow txAllStables)
+
+  txCounters :: Vec LinkCount (Signal GthTx (BitVector 64))
+  txCounters = zipWith txCounter transceivers.txClocks txResets2
+  txCounter :: Clock GthTx -> Reset GthTx -> Signal GthTx (BitVector 64)
+  txCounter txClk txRst = result
+   where
+    notInCCReset' = unsafeSynchronizer sysClk txClk notInCCReset
+    result =
+      regEn
+        txClk
+        txRst
+        enableGen
+        counterStartUgn
+        notInCCReset'
+        (countSucc <$> result)
   -- see NOTE [magic start values]
 
   -- rxFifos =