[skip ci] GTH: make TX_OUTCLK_SOURCE configurable

This allows us to directly use the GTH reference clock in logic, by selecting TXPLLREFCLK_DIV1, and do the FincFdec test on all nodes without extra cables.
bittide · Jul 2, 2024 · 6ebe6f7 · 6ebe6f7
1 parent 280a540
commit 6ebe6f7
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Showing 4 changed files with 19 additions and 16 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs b/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs
@@ -231,7 +231,7 @@ fincFdecTests diffClk controlledDiffClock spiIn =
     ) =
     gthCore
       @GthTx @GthRx @Ext250 @Basic125 @GthTx @GthRx
-      "X0Y10" "clk0"
+      "X0Y10" "clk0" "TXPLLREFCLK_DIV1"
       (pure 0) (pure 0) -- rxN and rxP
       clk
       (delayReset Asserted clk reset_all_out_sig) -- reset_all

diff --git a/bittide/src/Bittide/Transceiver.hs b/bittide/src/Bittide/Transceiver.hs
@@ -482,7 +482,7 @@ transceiverPrbsWith gthCore opts args@Input{clock, reset} =
   ( txN, txP, txClock, rxClock, rx_data0, reset_tx_done, reset_rx_done, tx_active
    , rxCtrl0, rxCtrl1, rxCtrl2, rxCtrl3 )
     = gthCore
-        args.channelName args.clockPath
+        args.channelName args.clockPath "TXOUTCLKPMA"
         args.rxN
         args.rxP
 

diff --git a/bittide/src/Clash/Cores/Xilinx/GTH/BlackBoxes.hs b/bittide/src/Clash/Cores/Xilinx/GTH/BlackBoxes.hs
@@ -43,17 +43,19 @@ gthCoreBBF _isD _primName _args _resTys = pure $ Right (bbMeta, bb)
   bb :: BlackBox
   bb = BBFunction (show 'gthCoreTF) 0 gthCoreTF
 
+-- | Number of constraints gthCore has
 nConstraints :: Int
 nConstraints = 6
 
-nNameArgs :: Int
-nNameArgs = 2
+-- | Number of "parameters" (non Signal arguments) gthCore has
+nParamArgs :: Int
+nParamArgs = 3
 
 -- | Instantiate IP generated with 'gthCoreTclTF'
 gthCoreTF :: HasCallStack => TemplateFunction
 gthCoreTF =
   TemplateFunction
-    [0..10]
+    [0..15]
     (const True)
     gthCoreBBTF
 
@@ -71,7 +73,7 @@ gthCoreBBTF bbCtx
     , _gtwiz_userdata_tx_in  -- " ::: Signal txUser2 (BitVector (ChansUsed*TX_DATA_WIDTH))
     , _txctrl2_in  -- " ::: Signal txUser2 (BitVector (ChansUsed*TX_DATA_WIDTH/8))
     , _gtrefclk0_in  -- " ::: Clock refclk0
-    ] <- drop (nConstraints + nNameArgs) $ map fst (DSL.tInputs bbCtx)
+    ] <- drop (nConstraints + nParamArgs) $ map fst (DSL.tInputs bbCtx)
   , [tResult] <- map DSL.ety (DSL.tResults bbCtx)
   , [gthCoreName] <- N.bbQsysIncName bbCtx
   = do
@@ -157,7 +159,7 @@ gthCoreBBTF bbCtx = error ("gthCoreBBTF, bad bbCtx:\n\n" <> ppShow bbCtx)
 gthCoreTclTF :: HasCallStack => TemplateFunction
 gthCoreTclTF =
   TemplateFunction
-    [0,1] -- used arguments
+    (fmap (nConstraints+) [0,1,2]) -- used arguments
     (const True)
     gthCoreTclBBTF
 
@@ -167,16 +169,16 @@ gthCoreTclBBTF ::
   State s Doc
 gthCoreTclBBTF bbCtx
   | [gthCoreName] <- N.bbQsysIncName bbCtx
-  , (exprToString -> Just channelNm,_,_) : (exprToString -> Just refClkNm,_,_) : _
+  , (exprToString -> Just channelNm,_,_) : (exprToString -> Just refClkNm,_,_) : (exprToString -> Just txOutClkSrc,_,_) : _
     <- drop nConstraints (N.bbInputs bbCtx)
-  = pure (renderTcl [IpConfigPurpose $ ipConfig gthCoreName channelNm refClkNm ])
+  = pure (renderTcl [IpConfigPurpose $ ipConfig gthCoreName channelNm refClkNm txOutClkSrc])
   where
-  ipConfig nm channelNm refClkNm =
+  ipConfig nm channelNm refClkNm txOutClkSrc =
     (defIpConfig "gtwizard_ultrascale " "1.7" nm){
-      properties = props channelNm refClkNm
+      properties = props channelNm refClkNm txOutClkSrc
     }
 
-  props channelNm refClkNm =
+  props channelNm refClkNm txOutClkSrc =
     [ property @Text "CHANNEL_ENABLE"                        (fromString channelNm)
     , property @Text "LOCATE_COMMON"                         "CORE"
     , property @Text "LOCATE_IN_SYSTEM_IBERT_CORE"           "NONE"
@@ -216,6 +218,7 @@ gthCoreTclBBTF bbCtx
 
     , property @Text "TX_REFCLK_FREQUENCY"                   "250"
     , property       "TX_REFCLK_SOURCE"                      (BraceTcl @Text $ fromString $ unwords [channelNm, refClkNm])
+    , property @Text "TX_OUTCLK_SOURCE"                      (fromString txOutClkSrc)
 
     , property @Text "TX_DATA_ENCODING"                      "8B10B"
     , property @Text "TX_INT_DATA_WIDTH"                     "40"

diff --git a/bittide/src/Clash/Cores/Xilinx/GTH/Internal.hs b/bittide/src/Clash/Cores/Xilinx/GTH/Internal.hs
@@ -25,10 +25,9 @@ type GthCore txUser2 rxUser2 refclk0 freerun txS rxS serializedData =
   , KnownDomain txS
   , KnownDomain rxS
   ) =>
-  String ->
-  -- ^ channel
-  String ->
-  -- ^ refClkSpec
+  String ->    -- ^ channel
+  String ->    -- ^ refClkSpec
+  String ->    -- ^ TX_OUTCLK_SOURCE must be one of [TXOUTCLKPCS, TXOUTCLKPMA, TXPROGDIVCLK, TXPLLREFCLK_DIV1, TXPLLREFCLK_DIV2]
   "gthrxn_in" ::: Signal rxS serializedData ->
   "gthrxp_in" ::: Signal rxS serializedData ->
   "gtwiz_reset_clk_freerun_in" ::: Clock freerun ->
@@ -55,6 +54,7 @@ gthCore :: GthCore txUser2 rxUser2 refclk0 freerun txS rxS (BitVector 1)
 gthCore
   !_channel
   !_refClkSpec
+  !_txOutClkSrc
   !_gthrxn_in
   !_gthrxp_in