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Add sim to vex risc ethernet
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lmbollen committed Dec 4, 2024
1 parent a239b18 commit 6fb0f86
Showing 1 changed file with 44 additions and 1 deletion.
45 changes: 44 additions & 1 deletion bittide-instances/src/Bittide/Instances/Pnr/Ethernet.hs
Original file line number Diff line number Diff line change
Expand Up @@ -13,8 +13,10 @@ import Clash.Explicit.Reset.Extra
import Clash.Prelude (HiddenClockResetEnable, withClockResetEnable)

import Clash.Cores.UART (ValidBaud)
import Clash.Cores.UART.Extra
import Clash.Cores.Xilinx.Ethernet.Gmii
import Clash.Cores.Xilinx.Unisim.DnaPortE2 (simDna2)
import Clash.Explicit.Testbench
import Protocols
import VexRiscv

Expand All @@ -26,11 +28,34 @@ import Bittide.ProcessingElement
import Bittide.Wishbone
import Protocols.Idle

-- Simulation imports
-- import Bittide.ProcessingElement.Util
-- import Bittide.SharedTypes
-- import Language.Haskell.TH
-- import Project.FilePath
-- import System.FilePath

type Baud = 921_600

-- Simulation baud rate
-- type Baud = MaxBaudRate Basic125

baud :: SNat Baud
baud = SNat

sim :: IO ()
sim =
uartIO @Basic125B stdin stdout baud $ Circuit go
where
go (uartRx, _) = (pure (), uartTx)
where
(_, uartTx, _, _) =
vexRiscEthernet
clockGen
resetGen
(clockToDiffClock clockGen)
(pure $ unpack 0, uartRx, pure $ unpack 0)

{- | Instance containing:
* VexRiscv CPU
* UART
Expand All @@ -45,7 +70,7 @@ vexRiscGmii ::
, KnownDomain tx
, KnownNat (DomainPeriod logic)
, 1 <= DomainPeriod logic
, ValidBaud logic 921600
, ValidBaud logic Baud
) =>
SNat gpioWidth ->
Clock logic ->
Expand Down Expand Up @@ -126,9 +151,27 @@ vexRiscGmii SNat sysClk sysRst rxClk rxRst txClk txRst fwd =
:> 0b1001
:> Nil
)
-- Comment out for simulation
(Undefined @(DivRU (256 * 1024) 4))
(Undefined @(DivRU (64 * 1024) 4))

{- FOURMOLU_DISABLE -} -- Fourmulu removes indentation
-- Uncomment for simulation
-- (Reloadable $ Blob iMem)
-- (Reloadable $ Blob dMem)

-- (iMem, dMem) =
-- $( do
-- root <- runIO $ findParentContaining "cabal.project"
-- let
-- elfDir = root </> firmwareBinariesDir "riscv32imc-unknown-none-elf" Release
-- elfPath = elfDir </> "smoltcp_client"
-- iSize = 256 * 1024 -- 256 KB
-- dSize = 64 * 1024 -- 64 KB
-- memBlobsFromElf BigEndian (Just iSize, Just dSize) elfPath Nothing
-- )
{- FOURMOLU_ENABLE -}

vexRiscEthernet ::
Clock Basic125B ->
Reset Basic125B ->
Expand Down

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