Trying to change sync node reset detection to work better for FPGA 7.

bittide · Oct 15, 2024 · 89ab9a9 · 89ab9a9
1 parent 39f41b5
commit 89ab9a9
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs
@@ -31,6 +31,7 @@ module Bittide.Instances.Hitl.SwCcTopologies (
 ) where
 
 import Clash.Explicit.Prelude hiding (PeriodToCycles)
+import Clash.Explicit.Signal.Extra (changepoints)
 import qualified Clash.Explicit.Prelude as E
 import Clash.Prelude (withClockResetEnable)
 
@@ -933,12 +934,13 @@ swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso =
   --     $ stickyBits (SNat @(PeriodToCycles Basic125 (Seconds 2))) testEnding
 
   -- Workaround for tests not resetting properly???
+  syncNodeProbablyWorking = changepoints sysClk testReset enableGen syncIn
   syncNodeEnteredReset =
     trueFor
       (SNat @(Milliseconds 25))
       sysClk
       testReset
-      (not <$> syncIn)
+      (not <$> syncNodeProbablyWorking)
   syncNodePrevEnteredReset =
     sticky sysClk testReset syncNodeEnteredReset