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Use transceiver clocks in FINC/FDEC tests #538

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Use transceiver clocks in FINC/FDEC tests #538

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559b5d0
Use transceiver clocks in FINC/FDEC tests
hiddemoll Jun 5, 2024
da910b0
Change system clock frequecy to 125 MHz to match transceiver tx clock
hiddemoll Jun 6, 2024
b7b3fa6
Add wrapper for gthResetManager which does not check rx domain
hiddemoll Jun 11, 2024
8e809e6
Make testDone and testSuccess sticky
hiddemoll Jun 10, 2024
cbe604d
Add debug ILA
hiddemoll Jun 6, 2024
cb3ddc5
Split ILA capture in separate capture conditions
hiddemoll Jun 10, 2024
bf777f4
Change GTH reference frequency to 250MHz - TODO change Si53xx config
leonschoorl Jul 2, 2024
a6881f4
GTH: make TX_OUTCLK_SOURCE configurable
leonschoorl Jul 2, 2024
5c96f39
Add clock configurations for 250 MHz
hiddemoll Jul 2, 2024
faf689f
Change external clock frequency to 250 MHz in all bittide instances
hiddemoll Jul 2, 2024
8a33391
Remove unused callistoSpi instance
hiddemoll Jul 2, 2024
b7d7074
Remove references to unused 200 MHz clock configurations
hiddemoll Jul 2, 2024
d842378
Add debug.json for fincFdecTests
hiddemoll Aug 9, 2024
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2 changes: 1 addition & 1 deletion .github/synthesis/all.json
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
{"top": "boardTestExtended", "stage": "test", "targets": "All" },
{"top": "boardTestSimple", "stage": "test", "targets": "All" },
{"top": "extraProbesTest", "stage": "test", "targets": "Specific [0]" },
{"top": "fincFdecTests", "stage": "test", "targets": "Specific [-1]"},
{"top": "fincFdecTests", "stage": "test", "targets": "All" },
{"top": "fullMeshHwCcTest", "stage": "test", "targets": "All" },
{"top": "fullMeshHwCcWithRiscvTest", "stage": "test", "targets": "All" },
{"top": "fullMeshSwCcTest", "stage": "test", "targets": "All" },
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3 changes: 3 additions & 0 deletions .github/synthesis/debug.json
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@@ -0,0 +1,3 @@
[
{"top": "fincFdecTests", "stage": "test", "targets": "All"}
]
10 changes: 3 additions & 7 deletions bittide-instances/data/constraints/fincFdecTests.xdc
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Expand Up @@ -19,22 +19,18 @@
#
# The data wire of the external reset button is connected to PMOD1_3.


# CLK_125MHZ
set_property BOARD_PART_PIN sysclk_125_p [get_ports {CLK_125MHZ_p}]
set_property BOARD_PART_PIN sysclk_125_n [get_ports {CLK_125MHZ_n}]

# USER_SMA_CLOCK
set_property -dict {IOSTANDARD LVDS PACKAGE_PIN D23} [get_ports {USER_SMA_CLOCK_p}]
set_property -dict {IOSTANDARD LVDS PACKAGE_PIN C23} [get_ports {USER_SMA_CLOCK_n}]
set_property BOARD_PART_PIN sma_mgt_refclk_n [get_ports {SMA_MGT_REFCLK_C_n}]
set_property BOARD_PART_PIN sma_mgt_refclk_p [get_ports {SMA_MGT_REFCLK_C_p}]

# Vivado marks all clocks as related by default. Our external clocks are not
# though, which means that we need to explicitly mark them as unrelated (or
# "asynchronous").
set_clock_groups \
-asynchronous \
-group [get_clocks -include_generated_clocks {CLK_125MHZ_p}] \
-group [get_clocks -include_generated_clocks {USER_SMA_CLOCK_p}]
-group [get_clocks -include_generated_clocks {SMA_MGT_REFCLK_C_p}]

# GPIO_LED_0_LS
set_property BOARD_PART_PIN GPIO_LED_0_LS [get_ports {done}]
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10 changes: 5 additions & 5 deletions bittide-instances/src/Bittide/Instances/Domains.hs
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Expand Up @@ -13,23 +13,23 @@ import Bittide.Arithmetic.Time
import Bittide.ClockControl
import Data.Proxy

createDomain vXilinxSystem{vName = "Basic25", vPeriod = hzToPeriod 25e6}
createDomain vXilinxSystem{vName = "Basic50", vPeriod = hzToPeriod 50e6}
createDomain vXilinxSystem{vName = "Basic100", vPeriod = hzToPeriod 100e6}
createDomain vXilinxSystem{vName = "Basic125", vPeriod = hzToPeriod 125e6}
createDomain vXilinxSystem{vName = "Basic125A", vPeriod = hzToPeriod 125e6}
createDomain vXilinxSystem{vName = "Basic125B", vPeriod = hzToPeriod 125e6}
createDomain vXilinxSystem{vName = "Basic199", vPeriod = hzToPeriod 199e6}
createDomain vXilinxSystem{vName = "Basic200", vPeriod = hzToPeriod 200e6}
createDomain vXilinxSystem{vName = "Basic25", vPeriod = hzToPeriod 25e6}
createDomain vXilinxSystem{vName = "Basic300", vPeriod = hzToPeriod 300e6}
createDomain vXilinxSystem{vName = "Basic50", vPeriod = hzToPeriod 50e6}
createDomain
vXilinxSystem{vName = "Basic625", vPeriod = hzToPeriod 625e6, vResetKind = Asynchronous}
createDomain
vXilinxSystem{vName = "Ext125", vPeriod = hzToPeriod 125e6, vResetKind = Asynchronous}
createDomain
vXilinxSystem{vName = "Ext200", vPeriod = hzToPeriod 200e6, vResetKind = Asynchronous}
createDomain vXilinxSystem{vName = "Ext200A", vPeriod = hzToPeriod 200e6}
createDomain vXilinxSystem{vName = "Ext200B", vPeriod = hzToPeriod 200e6}
vXilinxSystem{vName = "Ext250", vPeriod = hzToPeriod 250e6, vResetKind = Asynchronous}
createDomain vXilinxSystem{vName = "Ext250A", vPeriod = hzToPeriod 250e6}
createDomain vXilinxSystem{vName = "Ext250B", vPeriod = hzToPeriod 250e6}
createDomain
vXilinxSystem{vName = "Ext300", vPeriod = hzToPeriod 300e6, vResetKind = Asynchronous}
createDomain vXilinxSystem{vName = "External", vPeriod = hzToPeriod 200e6}
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