Make all GTH tx interfaces operate in the same domain #688
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| (N.Clock _, N.Clock _) -> True | ||
| (N.ClockN _, N.ClockN _) -> True | ||
| (N.Reset _, N.Reset _) -> True | ||
| (N.Enable _, N.Enable _) -> True |
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Why doesn't this compare domains? Could you add the explanation in a comment?
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Let's get this merged, add a comment in another PR.
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What this functions gets something like: Clock rxUser2 and Clock GthRx
So the right side is a concrete monomorphic type, but the left side still contains a type variable.
If you really want to properly check this, you'd have to do unification of the type variables over all the ports together.
And you can't do a simple per port check like this.
| { txOutClock :: Clock tx1 | ||
| -- ^ TODO |
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We can delete this right? The clock is generated outside of this block.
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txOutClock can not be deleted.
It's only connected one of the channels.
But on that one it's the source that feeds the "user clock network", which is what creates the txClock(2) used for everything.
| , rxOutClock :: Clock rx1 | ||
| -- ^ TODO |
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Similar as for the tx side, but here all of them are actually used individually because all domains are different.
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Before merging: please squash the formatting commits into parent(s). Edit: done |
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To make it easier to understand which signal to into ilaPlotSetup
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Intermittent failures for link related tests. Something is wrong.. Edit: happy to report that switching to the Xilinx RX/TX black boxes plus
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Let's keep the handwritten implementation in the history in case we need it
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This PR moves all transceiver TX interfaces to the same domain, instead of separate domains with (potentially) small phase offsets.
Note that the RX interfaces are in separate domains. (by design)
Background
In typical applications either:
Bittide is unique (?) in that we want an asymmetric setup: all the transmit domains should be the (exact) same, while receive domains remain independent. Because this is not covered by the typical use cases, we need to manually implement clock logic instead of relying on high-level Xilinx primitives.
Up to now, we've configured the transceivers as if all links were independent. Still, we provided the same reference clock to all individual links. In practice this would therefore amount to the asymmetric case. The problem is that static timing analysis will not apply across these domains, and we would therefore need clock domain crossing logic (FIFOs) to satisfy our design rule checks. This is for good reasons though: if we cannot apply STA, we cannot guarantee the sequential/digital abstraction and therefore risk failing bitstreams.
Up to now, this hasn't mattered much: for our experiments we haven't critically relied on the transmit domain being exactly equal. With the on-FPGA switch demo around the corner, we would like to get rid of the separate domains, hence this PR.
Old situation
New situation
Future work
There is now a whole bunch of redundant code dealing with n domains, which can be simplified. Preferably we'd do this after merging #654, as that PR will end up deleting a lot of code anyway.