Simple-32bit-ALU-Design

An implementation of a simple 32 bit ALU using verilog with working zero delay simulations.

To run:

$ verilog alu_zero.v

$ ./a.out

Name		Name	Last commit message	Last commit date
Latest commit History 25 Commits
Schematics		Schematics
Verilog		Verilog
README.md		README.md

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