Implement pause support for RISC-V

see-also: https://github.com/torvalds/linux/blob/84186fcb834ecc55604efaf383e17e6b5e9baa50/arch/riscv/include/asm/vdso/processor.h#L9
boostorg · Oct 24, 2023 · 38fa369 · 38fa369
1 parent 6ec7f68
commit 38fa369
Showing 1 changed file with 10 additions and 0 deletions.
diff --git a/include/boost/atomic/detail/pause.hpp b/include/boost/atomic/detail/pause.hpp
@@ -48,6 +48,16 @@ BOOST_FORCEINLINE void pause() BOOST_NOEXCEPT
     __asm__ __volatile__("pause;" : : : "memory");
 #elif (defined(__ARM_ARCH) && __ARM_ARCH >= 8) || defined(__ARM_ARCH_8A__) || defined(__aarch64__)
     __asm__ __volatile__("yield;" : : : "memory");
+#elif defined(__riscv) && __riscv_xlen == 64
+#if defined(__riscv_zihintpause)
+    __asm__ __volatile__("pause" : : : "memory");
+#elif defined(__riscv_muldiv)
+    /* In lieu of a halt instruction, induce a long-latency stall. */
+    __asm__ __volatile__("div %0, %0, zero" : "=r" (dummy));
+#else
+    /* Encoding of the pause instruction */
+    __asm__ __volatile__ (".4byte 0x100000F");
+#endif
 #endif
 #endif
 }