GitHub - buhman/cpu: FPGA-synthesizable RISC-V implementation

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Name	Name	Last commit message	Last commit date
Latest commit buhman branch prediction pipelining bug: data_hazard vs prediction pc Mar 25, 2021 f80ecb6 · Mar 25, 2021 History 38 Commits
sim	sim	sim_main: co-simulate with C implementation	Mar 25, 2021
tb	tb	sim_main: co-simulate with C implementation	Mar 25, 2021
test	test	add immediate generation test	Mar 25, 2021
.gitignore	.gitignore	sim_main: co-simulate with C implementation	Mar 25, 2021
Makefile	Makefile	branch_predict: replace with branch table buffer	Mar 24, 2021
btb.v	btb.v	reduce alu critical path	Mar 24, 2021
control.v	control.v	reduce alu critical path	Mar 24, 2021
control.vh	control.vh	trap signaling	Mar 19, 2021
cpu.v	cpu.v	branch prediction pipelining bug: data_hazard vs prediction pc	Mar 25, 2021
csr_reg.v	csr_reg.v	rework trap handling, flushes, and counters	Mar 21, 2021
csr_reg.vh	csr_reg.vh	rework trap handling, flushes, and counters	Mar 21, 2021
decode.v	decode.v	pipeline state bug: un-bubble id_ex__pc	Mar 24, 2021
dmem.v	dmem.v	initial 5-stage pipeline with forwarding unit	Mar 18, 2021
dmem_decode.v	dmem_decode.v	move dmem word decoding to the writeback stage	Mar 18, 2021
dmem_encdec.vh	dmem_encdec.vh	move dmem word decoding to the writeback stage	Mar 18, 2021
dmem_encode.v	dmem_encode.v	move dmem word decoding to the writeback stage	Mar 18, 2021
execute.v	execute.v	trap handling bug: epc should be the instruction that trapped	Mar 24, 2021
execute.vh	execute.vh	initial 5-stage pipeline with forwarding unit	Mar 18, 2021
fetch.v	fetch.v	branch prediction pipelining bug: data_hazard vs prediction pc	Mar 25, 2021
hazard.v	hazard.v	forwarding bug: classify RD_SRC_CSR as a data hazard	Mar 24, 2021
imem.v	imem.v	add data hazard unit	Mar 18, 2021
int_alu.v	int_alu.v	reduce alu critical path	Mar 24, 2021
int_alu.vh	int_alu.vh	reduce alu critical path	Mar 24, 2021
int_reg.v	int_reg.v	csr_reg: add performance counters, trap_return, and mtvec	Mar 20, 2021
jump.v	jump.v	improve instruction misalign trap handling	Mar 24, 2021
jump.vh	jump.vh	reduce alu critical path	Mar 24, 2021
mem_branch.v	mem_branch.v	trap handling bug: epc should be the instruction that trapped	Mar 24, 2021
sigma.pcf	sigma.pcf	initial 5-stage pipeline with forwarding unit	Mar 18, 2021
state.vh	state.vh	branch prediction pipelining bug: data_hazard vs prediction pc	Mar 25, 2021
top.v	top.v	int_reg: infer memory	Mar 19, 2021
writeback.v	writeback.v	rework trap handling, flushes, and counters	Mar 21, 2021
writeback.vh	writeback.vh	implement Zicsr	Mar 19, 2021