Merge pull request #512 from byuccl/randsoc_configs

Update datasets and allow randsoc start_idx

bfasst/flows/rand_soc_dumped.py

@@ -13,7 +13,7 @@
 class RandSocDumped(FlowNoDesign):
     """Flow to dump bels from random soc block designs with Isoblaze"""
 
-    def __init__(self, num_designs=1, part=None, randsoc_config_path=None):
+    def __init__(self, num_designs=1, part=None, randsoc_config_path=None, start_idx=0):
         # pylint: disable=duplicate-code
         super().__init__()
 
@@ -29,14 +29,17 @@ def __init__(self, num_designs=1, part=None, randsoc_config_path=None):
         assert randsoc_config_path.exists(), f"Config file {randsoc_config_path} does not exist"
 
         # Create all random designs
-        self.rand_soc_tool = RandSoC(self, num_designs=num_designs, config_path=randsoc_config_path)
+        self.rand_soc_tool = RandSoC(
+            self, num_designs=num_designs, config_path=randsoc_config_path, start_idx=start_idx
+        )
 
         # Build each random design
         for i, (design_tcl, contraints_tcl) in enumerate(
             zip(
                 self.rand_soc_tool.outputs["design_tcl"],
                 self.rand_soc_tool.outputs["impl_constraints_tcl"],
-            )
+            ),
+            start=start_idx,
         ):
             synth_tool = VivadoSynth(self, design_tcl.parent)
             synth_tool.synth_build["tcl_sources"] = [str(design_tcl)]

bfasst/tools/design_create/rand_soc.py

@@ -10,20 +10,21 @@
 class RandSoC(ToolBase):
     """Tool to create a random SoC"""
 
-    def __init__(self, flow, num_designs, config_path):
+    def __init__(self, flow, num_designs, config_path, start_idx=0):
         super().__init__(flow)
         self.build_path = BUILD_PATH / "rand_soc"
         self._my_dir_path = pathlib.Path(__file__).parent.resolve()
         self.num_designs = num_designs
         self.config_path = config_path
+        self.start_idx = start_idx
         self._init_outputs()
         self.rule_snippet_path = TOOLS_PATH / "design_create" / "rand_soc_rules.ninja.mustache"
 
     def create_build_snippets(self):
         rand_soc_pkg_files = list((GMT_TOOLS_PATH / "rand_soc" / "rand_soc").glob("**/*.py"))
         rand_soc_pkg_files.append(GMT_TOOLS_PATH / "rand_soc" / "main.py")
 
-        for i, design in enumerate(self.outputs["design_tcl"]):
+        for i, design in enumerate(self.outputs["design_tcl"], start=self.start_idx):
             design_dir_path = design.parent
             with open(self._my_dir_path / "rand_soc_build.ninja.mustache", "r") as f:
                 build = chevron.render(
@@ -43,7 +44,7 @@ def create_build_snippets(self):
     def _init_outputs(self):
         self.outputs["design_tcl"] = []
         self.outputs["impl_constraints_tcl"] = []
-        for i in range(self.num_designs):
+        for i in range(self.start_idx, self.start_idx + self.num_designs):
             design_dir_path = self.build_path / f"design_{i}"
             self.outputs["design_tcl"].append(design_dir_path / "design.tcl")
             self.outputs["impl_constraints_tcl"].append(design_dir_path / "impl_constraints.tcl")

resources/randsoc/dataset5.yaml

@@ -1,7 +1,7 @@
 flow: RandSocDumped
 
-num_designs: 6000
+num_designs: 6500
 
 part: xc7a200tlffv1156-2L
 
-randsoc_config_path: resources/randsoc/randsoc_configs/dataset5.yaml
+randsoc_config_path: resources/randsoc/randsoc_configs/dataset5.yaml

resources/randsoc/dataset6_test.yaml

@@ -0,0 +1,7 @@
+flow: RandSocDumped
+
+num_designs: 1600
+
+part: xc7a200tlffv1156-2L
+
+randsoc_config_path: resources/randsoc/randsoc_configs/dataset5.yaml

resources/randsoc/dataset6_train.yaml

@@ -0,0 +1,7 @@
+flow: RandSocDumped
+
+num_designs: 5500
+
+part: xc7a200tlffv1156-2L
+
+randsoc_config_path: resources/randsoc/randsoc_configs/dataset6_train.yaml

resources/randsoc/randsoc_configs/dataset6_train.yaml

@@ -0,0 +1,10 @@
+available_ip:
+  - class: Uartlite
+  - class: Accumulator
+  - class: AxiTimer
+  - class: Microblaze
+  - class: Dft
+  - class: Gpio
+
+min_ip: 3
+max_ip: 18